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TPS54424: Ask about TPS54424

Part Number: TPS54424

Hello support team,

 

My customer want to know following items:

 

  1. Need to know min and max value of Iss Soft-start current (typ 5uA) across temp and process variation
  2. How much is the FB terminal current?
  3. Valley current limit

Is there any limitation current? The customer is concerned when load is no load. They saw the output voltage is very large by off Low side FET due to exceeded the valley current limit.

 

Your help to be very appreciated.

 

Best regards,

Izumi Maruyama

  • Izumi-san,

    1. We may have additional unpublished data for Iss soft start current, I will check for it.
    2. The error amplifier input is extremely high impedance. We may not have test data on it except for leakage current. In any case, I would expect the input current to be only a few nA.
    3. TPS54424 uses peak current limit and valley current limit. Neither should come into play at no load conditions if your inductor is sized properly. There is also a low side sinking current limit of -3.4 A. That should not be an issue unless your peak to peak inductor current is > 6.8 A. That would indicate an unusually small inductor value that would not be appropriate for designs using TPS54424.
  • Hi Izumi-san,

    Some things I have to add to John's comments.

    1. The SS current should stay within 4.5 µA to 5.5 µA across temp and process. The current should be trimmed to within +/- 0.3µA at 25 °C in production and it changes by an additional +/- 0.2µA across temperature. However these are not the limits we test to in production so there is no guarantee.
    2. The typical FB leakage current is 4 nA at 25 °C and increases to ~30-40 nA typical at 150 °C.
    3. Can you share the schematic and some waveforms showing the customers issue?

    Best Regards,
    Anthony

  • Anthony-san,

     

    My customer has been asked additional questions about the TPS54424 as follows.

     

    1. How is the measurement condition of the Vfb (Regulated FB voltage)? Is it at Iout = 0A? Please let’s know the Iout value.
    2. How much the Load Regulation as shown Figure 38 can be deviated across temp range and process deviation? Can customer considers it be 5 times to the data on the Figure 38 to be good enough?
    3. The customer want to know min and max value of the Ioc_LS_snk (Low-side sinking current limit). Could you open them?

     

    Your support would be very appreciated.

     

    Best regards,

    Izumi Maruyama

     

  • Hi Izumi-san,

    Please see my comments below.

    1. How is the measurement condition of the Vfb (Regulated FB voltage)? Is it at Iout = 0A? Please let’s know the Iout value.
      The measurement condition is on the ATE open loop. This value should correlate to Iout = 0 A.
    2. How much the Load Regulation as shown Figure 38 can be deviated across temp range and process deviation? Can customer considers it be 5 times to the data on the Figure 38 to be good enough?
      Generally the load regulation does not vary across temperature and process. The regulated Vfb voltage specified in the electrical characteristics is what accounts for temperature and process variation. Adding 5x to the data in Figure 38 would be pretty conservative in my opinion. However load regulation can be impacted by PCB layout so it is important to have a good PCB layout to have the best load regulation.
    3. The customer want to know min and max value of the Ioc_LS_snk (Low-side sinking current limit). Could you open them?
      Based on the data we have, I recommend using a min and max of -4.4 A and -2.5 A respectively.

    Best Regards,
    Anthony