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UCC24624: SR1 Vgs waveform is changing every cycle

Part Number: UCC24624

Hi Bing-san,

SR1 Vgs waveform is changing every cycle.

SR2 Vgs waveform is good because 100ohms added to VSS to SR2 Mosfet Source.

My customer asked me, how to stable SR1 Vgs waveform ?

Or can you explain detail of that it is still keeping best efficiency?

Waveform is attached,

SR1 Vgs waveform.pdf

  • Hi Doi-san,

    Nice hearing from you. Do you have a copy of the layout file we could review? Could you provide a zoomed in picture of the SR1 Vds waveform? We would like to know the shape of the Vds waveform when the MOSFET is conducting. You will want to use a small voltage scale to see the shape.

    Best Regards,
    Ben Lough
  • No.

    I have to get answer Today.

    Otherwise we will lost.

  • Hi, Doi-san,
    This is expected from the IC operation.
    UCC24624 operates with the proportional gate drive. It reduces the gate voltage to increase the SR conduction voltage. This eventually helps to improve the conduction time the SR and reduces the SR loss.
    The control of the proportional gate drive comes from its VDS voltage. When its voltage is above -35mV, the proportional gate drive kicks in and start to reduce the gate voltage.
    In your waveforms, the two cycles are just at the edge where the proportional gate drive threshold. Therefore, at one cycle, it hits the threshold and the other cycle, it misses the threshold. And because the LLC operates above the resonant frequency, the high di/dt on the secondary side immediately cause the SR to turn off. Therefore, in the one cycle where the proportional gate drive doesn't kick in, the SR turns off immediately without seeing the gate drive voltage reduces.
    This is the normal operation and it is expected in this operation mode.
    If you increase or decrease the load, you should see this behavior go away.
    Let me know if you have any further questions.
    Thanks.
    Bing
  • Bing-san,

    My customer wonder if the control that changes the waveform every such cycle does not degrade efficiency.
    Can you explain that control does not degrade efficiency?
  • Doi-san,

     If the operation is just the proportional gate drive kicking in or not, it should not affect the efficiency, since the SR controller is responding to the power stage correctly.

     However, I looked at your waveform in more details, and it appears that when the proportional gate drive is not enabled, SR turns off early.

     If you look into more details, you can see the SR is turned off right at the point where the proportional gate drive might be kicking in.

      It appears to me the SR is turned off early, so that it will hurt the efficiency on the SR conduction loss.

     I don't know exactly why the SR decide to turn off early. There are several possibilities.

    1. The bad layout. Once the SR controller enables the proportional gate drive, there are some current to pull the gate voltage low. If this current causes some noise on the voltage sensing, it might cause the SR to turn off early. Can you help to show the layout around this IC? Or are you using the daughter card?

    2. The di/dt on the SR causes enough offset voltage and causes the SR to turn off early. I have less confident on this since it happens at the flat portion of the current, where the di/dt is pretty small. To avoid this, you can simply add a resistor between VSS pin to PGND to increase the turn off threshold a little bit. I would suggest to start with 30ohm.

    Or you can level this alone since the impact on the efficiency is fairly small. It has 600ns of body diode conduction time on each two switching cycles. Given the switching frequency is about 130kHz. This would increase the conduction loss by ~0.1%.

    Let me know your thoughts.

    Thanks.

    Bing

  • Bing-san,

    They are swapping SR IC on their original ST micro SR board.

    So mainly wire lead connecting method.

    But you can not say it that is the reason why.

    Japanese maker have to get perfect result before making board.

    And they use 100 ohms between Vss and SR2 source.

    They are very pleased of SR2 waveform improved.

    If you request the resistor value change, teach me how to determine the value by looking what?

  • Hi, Doi-san,
    Since they already used the VSS resistor, there is no reason to add more resistor there.
    When they add the resistor, can you ask them to put the 100-ohm resistor between the VSS pin and PGND, and then use a thick wire to connect PGND to the middle of the two SR MOSFET. Please refer to the datasheet layout example for the details.
    They should be able to get the two channel SRs behave about the same.
    Let me know what you find out.
    Thanks.
    Bing
  • Bing-san,

    I understand. But you know the distance of both Mosfets Source is always long.

    Does 120 ohms or 150 ohms is not good solution?

    Never use over 100 ohms value?

  • Sorry I press the wrong button.
    Yes, you can use 120 or 150 ohm. The only reason I mention 100 ohm because in your message, you said they were using 100 ohm resistor.
    When you do the layout, try to put the resistor in the middle of the two FETs so that the layout is relatively symmetrical for both of them. And I hope they have a big piece of copper connecting between two MOSFETs so that the inductance and resistance can be minimized.
    Let me know what you found out.
    Thanks.
    Bing