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Hello Bob,
The startup current is drawn by UC2843 during the Vdd voltage is ramping towards the UVLO threshold.
When VDD reaches the UVLO turnON threshold there is a transition when the controller requires more current to charge the internal bias for Vref(to provide power for the internal circuit), drive the oscillator for OUTPUT, charge the SS caps, etc.
I do not think there is anything unexpected here.
Regards,
Sonal
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