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TPS7A19: TPS7A19 Vdelay vs Vin

Kai Nomiyama
Expert 5545 points
Part Number: TPS7A19

Hi Team,

I have  a question about TPS7A19 Vdelay vs Vin.

TPS7A19 datasheet mentions "The voltage at the DELAY pin must be lower than the Vin voltage".

when there is Vin short to GND event, depending on Cdelay and ⊿dVin/dt, my customer worries that Vdelay becomes higher than Vin and it violates datasheet abso max spec.

Are there any good way to prevent Vdelay > Vin externally?

in addition, do you have tdelay time constant and Vthreshold of any pin that Vdelay goes down from 1V?

regards,

Kai

  • 0
    TI__Guru 55940 points
    Hi Kai,

    The best method would be to prevent Vin from being shorted to GND until after the output rail is fully discharged; however, it sounds like you are expecting there to be a way that your input rail shorts to GND with a fast slew rate while the output is enabled. Out of curiosity, what would cause this short to occur?

    If you were to place a diode in series with the LDO between the upstream power supply and the input capacitor of the LDO you would be able to reduce the risk of violating the Absolute Maximum ratings for any of the pins. This is because when a short occurs on your input rail, the diode would allow the input capacitor to remain charged for a time. This would keep the input voltage local to the IN pin within the Absolute Maximum ratings.

    Very Respectfully,
    Ryan