CCS/UCD3138064A: Some setting questions about oversample with PSFB topology PCM control, oversample related registers

Hello Cheng

See my response below

1.  As parameters shown above, Is it correct that UCD will sample 8 times at 12%, 24%, 36%, 48%,60%, 72%, 84%, 96% in one period as figure1?

This is correct

2. To continue the question 1 above, Is it correct  that average result will be calculated after 96% sample trigger and then using this front end data for filter calculation

Actually not quite. What you are actually doing is sending more frequent sample triggers to the front end. Instead of sending one sample trigger per period, you are sending 8 samples triggers per period. The EADC in the front end is continuously sampling the difference between the set-point and the input pins, either every 8MHz or 16MHz. Each time it receives a sample trigger from a DPWM, it the front end pushes the most recent sample into the filter. The filter takes around 520ns to process the sample. So you are just updating the filter more frequently using this feature, which is effectively a sort of averaging. I guess it really only effects the integrator stage of the filter (and the D stage if you are using Dalpha).

3. To continue the question 1 above, only 4% period time left can be used for filter or other calculation in one period. How to know time is enough or not

if 4% of your period is greater than 520ns, then you have enough time

4. How much time for filter to calculate PID and get the result?

520ns

5. Is it a good way to use oversampling in PSFB PCM control? How to determine the trigger time interval (from start to end) by PSFB PCM control? What is the side effect that may happen?

Not sure about this one, will have to ask one of my colleagues in Dallas. Can you eloborate on what you mean by "How to determine the trigger time interval (from start to end) by PSFB PCM control"

Best Regards

Cormac

Hi Cheng
on 2: this is correct. you are just feeding new samples of the error signal into the filter more often. There is also different averaging that can be done at the front end: averaging the samples before they are fed into the filter. See www.ti.com/.../sniu028a.pdf, page 116.

on 5. I'll ask one of our hardware experts and get back to you. To ensure that the PID controller updates before the end of the period, the last sample should more than 520ns before the end of the period. So at 100kHz, the period is 10us, if you oversample 4 times, you want to make sure that the last sample is before the (10us - 520ns) = 9.48us mark.

Best regards
Cormac

Hi Cheng
Here is the response from the hardware expert:

For 100kHz, the filter still have enough time to calculate 4 times even it is placed at half period. But it can be placed later than half period. Placing 520ns before the end of period is sufficient to guarantee the PID is updated before the end of period. It is best to place the sample trigger closer to the end of the period, as close as possible without violating the rule that it needs to be at least 520ns from the end of the period

Hope this helps

Best Regards
Cormac