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LP8732-Q1: LP8732-Q1 - LDO stability

Part Number: LP8732-Q1

Hello Team, we have some questions on stability criteria of the LDOs:

Existing design is using output capacitor in total of more than 50uF ceramic.

  • Can we do stability measurements on LDO (similar what we did with buck) but missing feedback pin to do Bode Plot measurements?

  • How can we guarantee stability by given capacitor? According datasheet maximum of 2.7uF is specified

  • What happens when we hit the ILIMIT of the LDO during start-up? Will LDO switch off and re-cover? Which could happen during charging the capacitors.

 Many Thanks

Josef

  • Josef,

    We have had customers use larger capacitances than the 2.7uF that is in the datasheet without issue. The only thing to watch out for is the inrush current causing the LDO to hit current limit. This can be calculated using C = I / (dv/dt)

    So the maximum capacitance I would recommend is
    C = 0.4A / (15mV/us) = 26.7uF

    If the LDO hits current limit it will continue to regulate at the current limit, which can cause a drop in the output voltage. If the output voltage drops too low, then the regulator PGOOD signal will go low, which depending on the device settings could cause an interrupt or cause the PGOOD pin to go low. When the LDO is first enabled the regulator has 800us to reach its output voltage before the device checks for a PGOOD signal, so even if your slew rate is slowed down due to current limit it still may not cause PGOOD to change.

    You could use the same equation as above with your actual capacitance and the current limit to calculate what your actual slew rate would be (which should be lower than the devices fixed slew rate) and then from there see if you could reach your output voltage before the 800us is up.
  • Hello Mr Jakse,

    thank you for your answers.

    Regarding the worst case capacitance the application is using 66µF  with tolance (+10%) and over temperature (+3% at -40°C)

    Our startup measurements shows the current limit of 400mA is triggered during initial ramp up.

    LDO0 2.5Volt-rail is finished after 400µs

    LDO1 1.0Volt-rail is finished after 100µs

    Both durations are below the mentioned 800µs before PGOOD is checked during first startup.

    Do you agree that the reduction of slew-rate during initial ramp up is uncritical?

    For stability testing we connected a static load of 60mA ( 20% of 300mA) and applied a step to 240mA ( 80% of 300mA) with the capacitance connected during application.

    Voltage measurement at the output of LDOs show very small rise / drop during step, which is regulated fast to the typical output voltage.

    LDO0 2.5Volt-rail   20%->80%  drop of 10mV / 80%-20% rise of 12.5mV

    LDO1 1.0Volt-rail   20%->80%  drop of 10.5mV / 80%-20% rise of 13mV

    No oscillation, ringing or long regulation time observed.

    Would you agree that the stability is given even with the larger capacitance applied to the regulator?

    Thank you,

    A. Stengel



  • Mr. Stengel,

    Based on those transients the LDO looks stable.

    As for the slew rate I would agree that it is not critical, as long as you don't care about any interrupts that can be generated by hitting current limit. The scope shots you have shown are what I would expect, and are well withing the 800us window.

    400mA / 66uF = 6mV/us, 2.5V / 6mV/us = 416us which is close to what you have measured.
  • Mr. Jakse,

    thanks for your feedback.

    Also on our side we see no issue on stability.

    We do not use the interrupts from the LP8732 on startup. Due to this we have no problem with the startup. Also the 800us window is far away.

    Can we therefore use the voltage regulator in the application with this wiring?

    Thanks for your help.

    A. Stengel

  • Mr. Stengel,

    Yes you should be able to use the voltage regulator in this application.