TPS54388-Q1: what will happen if Sync/RT pin is pulled high when EN is high?

Alpha,

If the input voltage is above the UVLO, EN is high and the TPS54388-Q1 switching, then pulling RT/CLK high will cause the TPS54388_Q1 to switch at the lowest possible switching frequency. This will likely not damage TPS54388-Q1, but will certainly have adverse effects on your system. You will see very high peak to peak inductor currents and the output will go out of regulation with over voltage. I highly recommend that you:
1. Only connect an RT resistor directly from RT/CLK to GND with no other external connection for internal RT clock setting.
or
2. If you use an external clock, only apply it before the TPS54388-Q1 is enabled or once the TPS54388-Q1 has started regulating.
3. Once the external clock is applied, do not remove it while the TPS54388-Q1 is enabled.
4. Do not pull RT/CLK either high or low for long time duration (longer than is typical for the high or low state of an external clock.

TPS54388-Q1 expects ether that RT/CLK is internally regulated to 0.5 V and terminated to GND with an RT resistor or that an external clock is present in the acceptable frequency range. Any other condition will result in unwanted behavior.

TPS54388-Q1 dos not have any special pre-bias operating modes. It will attempt to discharge the pre-bias output thru the low side FET at re-start. There is a low side sinking current limit to prevent large discharge currents form occurring.