LM73606: Use case questions about limitations

Hello Shinya,

I have preserved your numbering in my response:

1) The maximum duty factor at full frequency depends on selected switching frequency. You can calculate this maximum duty factor using the min off-time, tOFF-MIN in the timing table, specification and your selected switching frequency. If this duty factor is too low to regulate output voltage, the part automatically reduces frequency achieving until duty factor reaches maximum duty factor, DMAX in the systems table. While this parameter has a minimum value of 97.5%, it is typically closer to 98.5% on the bench.

2) Which is the protection behavior, latched off or auto retry?
a)-1 UVLO – The part shuts down if input voltage is below its input under voltage threshold, actually controlled by VCC UVLO; See “Internal LDO, VCC_UVLO, and BIAS Input” in the feature description section of the datasheet. The enable pin may also be used as an input UVLO; see “Enable and UVLO” in feature description section of the datasheet
b)-2 UV/OV – The part signals output UV and OV using PG. See “Power-Good and Overvoltage Protection” in the feature description section of the datasheet. The part continues to attempt to regulate under these conditions.
c)-3 OCP – If overcurrent is reached, the part continues to operate at maximum current but reduced output voltage until feedback voltage falls below approximately 0.4 V, VHICCUP in the EC table. Once output voltage falls below this value and after a very short delay, the part will repeatedly shut down and retry. See “Overcurrent Short Circuit Protection” in the feature description section of the datasheet.
d)-4 Reached the max duty – The part continues to run unless input UVLO is activated or EN becomes low.

3) If some of 2) is latched, how can we return to a normal condition? There are no conditions that latch.

4) Is there a formula for how to calculate the min Vin vs Vout.
e.g.) Vin(min)=Vout/97.5% - this one works.

5) Is there a good explanation to understand how the OCP works for HS and LS each?
Both HS and LS current limit are cycle by cycle. The high side is turned off within tON-MIN after the HS CL threshold is reached, HIS_LIMIT. The low side is not allowed off – extending the next clock cycle – if LS current is above ILS_LIMIT.

6) Is there any startup sequence limitation during VCC/PVIN/EN? Is it possible to bias to EN before PVIN?
VCC is an output so will operate automatically – the chip’s internal sequencing will control this one. PVIN should be before BIAS since VCC can back-feed into PVIN.

Regards, Robert