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Original question:

TPS65911: Is pin HDRST also POWER ON disable condition

TPS65911: HDRST toggling

Josef Rypar47
Prodigy 240 points
Part Number: TPS65911

Hi Phil,

I've got another question regarding HDRST.

Consider situation when the system is turned on, HDRST input is low and all the output power rails are operating correctly. What happens when HDRST is toggled high and low again very quickly (say within 1ms)? Does the PMIC complete the power-off sequence correctly before turning on again? Or does it start the power on sequence again without having the output power rails completely discharged?

Thank you.

Josef

  • 0
    TI__Genius 17380 points

    Hi Josef,

    The PMIC will complete the power down sequence before powering back up. I found the cutoff for pulses to generate a shutdown event to be approximately 125 us.

    Scope shot below shows one of the regulators in yellow (I tested with both LDO4 and VIO on the TPS659114 OTP and they have the same behavior roughly) with a 50 mA load and HDRST in blue (scale is messed up because I forgot to set the attenuation, but it's a 1.8V signal).

    I found about a 4 ms delay between the rising edge of HDRST and LDO4 starting (the first power rail in this OTP). Note that for unloaded rails, they will not decay to 0 necessarily, it depends on the loading. That is why I added the 50 mA.

  • 0 in reply to Kevin LaRosa
    Prodigy 240 points
    Hi Kevin,
    many thanks for an accurate and prompt answer. From the above I understand that:
    1. The decay of the voltage rails depends solely on their loading and amount of connected capacitance.
    2. There is no active discharge circuitry (such as activation of low-side MOSFET in switching regulators) that would reliably force the output to 0 before turning on again.
    3. The regulators are simply turned off (as if disconnected from their rail).
    Can you please confirm the above statements?
    Thanks again!
    Regards,
    Josef
  • 0 in reply to Josef Rypar47
    TI__Genius 17380 points

    Hi Josef,

    The rails do have a discharge mechanism through internal pull down resistors.

    VIO, VDD1, and VDD2 have discharge resistors (50 Ω max) that are enabled when the rail is disabled but that won't guarantee 0 V on its own. For example, if VIO (3.3 V) has 121 uF of capacitance on its output then with a 50 Ω pull down it will reach approximately 1.7 V in the 4 ms before restarting if there is no load. The LDOs are typically 600 Ω when off (labeled as "internal resistance" in the datasheet instead of discharge resistance which made it a bit tougher to find), so it would be approximately 50 ms to decay halfway with no load.