TPS65094: DRVL and PGNDSNS route when FET is far from PMIC

zhuyt05

Prodigy 110 points

Part Number: TPS65094

Dear Sir,

I found PGNDSNS is sensitive signal and DRVL is aggressive signal in Layout Checklist.

In intel's design 560683-apl-rvp-crb-lpddr3-ti-tdk-rev2p0, DRVL is parallel to PGNDSNS,is it wrong?

over 6 years ago

0 Nick Jakse49 over 6 years ago

TI__Expert 4155 points

zhuyt05,

If that pink trace is PGNDSNS then I don't believe this is a mistake. The PGNDSNS trace should be routed like that so that it only connects to PGND at the FET. I can't tell from this picture, but I am assuming that there is a GND plane that the FET vias down to which gives the return loop a short and low resistance path back to the PowerPAD.

0 zhuyt05 over 6 years ago in reply to Nick Jakse49

Prodigy 110 points

Thank you for your reply!
You are right. There is a GND plane（on L9）and DRVL route is on BOTTOM（L10）.

Power management

Power management forum

TPS65094: DRVL and PGNDSNS route when FET is far from PMIC