TPS7B4253-Q1: Enable pin troubles

Friedl

Prodigy 180 points

Part Number: TPS7B4253-Q1
Other Parts Discussed in Thread: TPS7B4253EVM, , TINA-TI

Hello!

We are seeing a strange startup behavior when using the ENABLE pin while ADJ is already stable.

The setup is the TPS7B4253EVM:

TP1 (VIN) = 24V power supply

TP2 (EN) = Waveform generator, rectangle, 3.3V, periode 30s

TP3 (GND) = GND

TP4 (ADJ) = 3.3V

TP5+TP6 (VOUT + GND) = 1K resistor + scope probe

We see a rather strange ramp up of the output voltage. We'd expect a monotic ramp-up rather than what we see here:

Please advice.

over 6 years ago

0 Min Hudgins over 6 years ago

TI__Prodigy 515 points

Hello Friedl:

I suggest adding 10uF capacitor at the output. If you have tried and still have the same problem, let us know.

Regards,

Min Hudgins

0 Friedl over 6 years ago in reply to Min Hudgins

Prodigy 180 points

Hi!

The EVM has got already more than required as minimum installed - 22µF to be precise.

According to the datasheet:

I would rather want to reduce the capacitance for the final product.

0 Ryan Eslinger over 6 years ago in reply to Friedl

TI__Guru 55940 points

Hi Friedl,

TPS7B4253-Q1 has an internal clamp on Vadj that activates with a fast Vadj slew rate during startup. Since Vadj is already at its final value when you enable the regulator, the clamp is activated during your test.

The clamp will hold Vout at ~3 V temporarily when activated. The reason that your output voltage is reducing is because your resistive load is discharging the output capacitor while the clamp is active.

Very Respectfully,
Ryan