TPS65218: Warm Reset

If this is for an AM335x or AM437x application, then my recommendation is you follow the reference design and keep this pin wired to the processor.

The setting of GPIO as an input or output internal to the TPS65218D0 is controlled by DC12_RST.

By default, DC12_RST = 1b, which means GPIO3 is configured as warm-reset input to DCDC1 and DCDC2. The Warm Reset will be controlled by an output pin on the processor.

This feature is defined as follows:
"Using GPIO3 as Reset Signal to DCDC1 and DCDC2
With the DC12_RST bit set to 1, GPIO3 is an edge-sensitive reset input to the PMIC. The reset signal affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default whenever GPIO3 input transitions from high to low, while all other registers maintain their current values. DCDC1 and DCDC2 transition back to the default value following the SLEW settings, and are not power cycled. This function recovers the processor from reset events while in low-power mode."

In my opinion, it is not a good idea to short this input to GND, because DCDC1/2 could Warm Reset unexpectedly as a result of this pin always being set low.

If this is for another application, then please elaborate on the system so I can provide further guidance.