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UCC24612: Locked in Fault mode ?

Fabrice
Prodigy 50 points
Part Number: UCC24612

Dear all,

I have an issue testing this device.

When the duty cycle is incresead by a big step (let's say from 30 to 50 %), the device lock and SR is no more active even if I reduce duty cycle.

The only option is to remove vdd and power-it back on.

Is there a special mode explaining this "locked" behaviour and why it goes in ?

Thanks.

  • 0
    TI__Expert 8210 points
    Fabrice

    There is no latched fault response for UCC24612. There are several conditions where it will stop operating, and there is hysteresis to enable operation.

    UCC24612 has a frequency dependent sleep mode. When the frequency reduces below 12kHz UCC24612 is disabled. There is a hysteresis so it won't resume switching until the frequency exceeds 15kHz. Section 7.3.5 (page 21) of the UCC24612 datasheet goes into more detail about this. Please confirm if this is causing the issue you are seeing.

    Also please review to insure that REG voltage is above UVLO. During this big step please measure the voltage on this pin to make sure it does not drop below the UVLO turn off VREGOFF. There is a hysteresis for UVLO turn on, so please confirm that the voltage increases above turn on threshold VREGON.

    Best Regards,
    Eric
  • 0 in reply to Eric Faraci
    Prodigy 50 points
    Eric,

    thanks for your help.
    Frequency used is 32.5 kHz and is fixed.
    As suggested, I look at VREG.
    I saw about 10V on regular mode and about 15V (VDD) just after...
    I've also seen some spiks on VDD so I decided to add 10nF X7R filtering.
    Thinks are now working better but still some improvements to do.
    Finaly one last question : I'm going to filter VDD input, but is it also necessary to filter Vd ?

    Thanks again for your support.
    Fabrice
  • 0 in reply to Fabrice
    TI__Expert 8210 points
    Fabrice

    Glad to hear that you're making progress resolving this issue.

    Pin VD is used to measure the drain of the SR FET that UCC24612 is controlling. We don't recommend placing any capacitor from VD to GND. The snubber across the SR FET, which will connect from VD to VS pins, in addition to the internal control will provide sufficient filtering for any noise seen on this pin.

    Best Regards,
    Eric