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TPS65218D0: PGOOD failure by DVS

Kuramochi Tadahiko
Guru 28715 points
Part Number: TPS65218D0
Other Parts Discussed in Thread: AM3358,

Hi,

My customer is evaluating the TPS65218D0 and AM3358.

PGOOD failure occurs on DCDC2 when output voltage drops by DVS at light load as attached.

When output capacitor is below 50uF, this failure does not occur.

So, I think that the cause of this failure is slow discharge from DCDC2 output.

1. Is there any workaround for this failure?

    Though they have already confirmed to improve by STRICT = 0b setting, this can not be applied by restriction of AM3358 side.


2. Though DCDC2 output capacitor is recommended ~500uF on the datasheet, is this considered to use DVS function?

Best Regards,

KuramochiTPS65218D0 PGOOD Fail.xls

  • 0
    TI__Mastermind 30310 points
    TQ,

    The output capacitance for DCDC1/2 recommended in the datasheet is 10uF (min), 22uF (typical), 100uF (max) local capacitance near the output inductor.

    It is the processor side that requires additional capacitance (up to 500uF) distributed at the point(s)-of-load. If you can ensure the AM3358 still operates correctly with lower capacitance, then this is OK for the TPS65218D0.

    Why can't you use STRICT=0b for the AM3358? The STRICT=1b setting is only for AM437x processors, which is an additional security feature of the system. The AM3358 should have no issues when STRICT=1b.


    Another option would be to change the SLEW[2:0] setting, bits 2-0 in the SLEW Register (0x1A).

    The "window" of ignoring PGOOD signals internally is a fixed value. The default value for 0x1A is 0x06, and you could try changing this to 0x07 for "immediate" slewing that will only be limited by the output capacitance.

    Also, what is the starting voltage of DCDC2 and what is the ending voltage? If VDCDC2 = 1.35V and VDCDC2' = 0.9V, this could be too much voltage to drop in the "window" of time. You can go in steps, from 1.35V to 1.2V, then from 1.2V to 1.1V, then from 1.1V to 1.0V, and finally from 1.0V to 0.9V to avoid the issue.

    If this does not work, your only options would be: (1) Set STRICT=0b during negative DCDC2 transitions only, or (2) work with AM3358 team to reduce remote capacitance.
  • 0 in reply to Brian Berner
    Guru 28715 points

    Brian-san,

    Thank you for your advise.

    We'll try them.

    >Why can't you use STRICT=0b for the AM3358? The STRICT=1b setting is only for AM437x processors, which is an additional security feature of the >system. The AM3358 should have no issues when STRICT=1b.

    I think that STRICT=0b cannot be allowed because out of the the AM3358 voltage range as below.

    Best Regards,

    Kuramochi

  • 0 in reply to Kuramochi Tadahiko
    TI__Mastermind 30310 points
    Kuramochi-san,

    Another idea I had last night:

    Instead of using STRICT=0b you can sent PFM=0b for DCDC1/2 before changing the voltage. PFM is bit 7 of DCDC1 and DCDC2 register.

    PFM=0b will enter fPWM mode, so the DC-DC converter will switch every clock cycle and the low-side FET will "bleed" voltage from the output.

    You can set PFM=1b to resume PFM mode after the voltage transition is complete.