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LM5022: Current sense tolerance on paralleled devices

Robert van der Sanden
Prodigy 30 points
Part Number: LM5022
Other Parts Discussed in Thread: LM5176

We make use of the LM5022 in a Sepic converter, in a 3 phase interleaved configuration, following TI's advice as stated below:

(1) Use one LM5022 as the Master, and the other as the slave, by tying the slave's FB pin to GND, and it COMP pin to the master's COMP pin;
(2) Provide an external clock to each LM5022 to synchronize their switching to avoid beat frequency.
(3) If you want to interleave operation, you should provide 180 degree phase shifted clock signals to each LM5022. 

We provide 3 120 degree out of phase clocks. This works great.

Question: when the COMP pins are tied together, and the FET of each branch has it's own current sense resistor to each controller, the currents are not always equal in each branch. We see up to 20% difference in voltage on each current sense resistor at the point where the FETs turn off per branch.

What is the tolerance in the relation between the COMP pin voltage and the current at which the FETs are turned OFF. From the internal block diagram of the control IC there are two diodes and a resistive divider in between. What is the accuracy and temperature effect here?

Robert

  • 0
    TI__Guru 58761 points
    Hi
    The responsible engineer is out now. We will reply by 4/12
    Regards,
    EL
  • 0
    TI__Mastermind 21720 points
    Hi Robert,

    Thank you for reaching out with your question.

    When the LM5022 is configured as you mention the tolerance between the current per phase can be large. This is mainly due to the offset caused by the internal COMP to PWM offset and the internal attenuation that can be seen in the block diagram. These gain factors are not trimmed and will vary over temperature as well as from part to part. This is a common issue for peak current mode boost converters that are configured to operate in multiphase

    Is there a certain tolerance between the channels that you are trying to achieve?

    Thanks,

    Garrett
  • 0 in reply to Garrett Roecker
    Prodigy 30 points
    Hi Garrett,

    thanks for replying to my question. To keep the current sharing between the three branches within a reasonable limit, I would say max. 5 - 10% would be nice. If one current is 10% more than the others, there are already 20% more conduction losses in that branch, which causes thermal issues.

    Can you put a ballpark figure on the tolerances you mentioned? What should I think about? Can you make a split between trimming errors and thermal effects?

    Thanks!
    Robert
  • 0 in reply to Robert van der Sanden
    TI__Guru 58761 points
    Hi
    The responsible engineer is out of office now. He will reply by 4/23.
    Regards
    EL
  • 0 in reply to Robert van der Sanden
    TI__Mastermind 21720 points
    Hi Robert,

    Realistically it will pretty hard to achieve the 5% to 10% current sharing that you require with this setup. The main reason is that the COMP to PWM offset and internal attenuation vary a lot from part to part. In a single phase design this is not a problem as the COMP voltage adjusts itself to set the correct current level. To achieve better current sharing the board will need to be modified with some extra components.

    To achieve better current sharing I recommend following the application note linked below. This example uses the LM5176 but can be applied to any converter. The basic idea is that the external error amplifier is used to adjust the output voltage of the slave so that the current is shared between the phases properly. This approach should produce the current sharing that your application requires.
    www.ti.com/.../snva826.pdf

    Please let me know if you have any questions.

    Thanks,

    Garrett
  • 0 in reply to Garrett Roecker
    Prodigy 30 points
    An application support engineer of TI (Roberto Scibilia) has evaluated the design and made a calculation. He concluded a variation on the internal 1.4V bias of +/- 22% and a variation on slope compensation amplitude of +/- 25%. In the actual design, with our values of currents and sense resistors, the total variation of peak current can be up to +/- 60%.
    The circuit will be re-designed with a different control IC, better suited for parallel operation.