UCC28951-Q1: GENERAL STARTUP QUESTIONS

Dear Loy,

This is from my colleague comment as below,

Q1 – leaving the OUTE and OUTF pins open is ok. The ADELEF pin should be grounded if not used, our EVM uses a potential divider and a zero Ohm link to provide flexibility and this is a useful option. The DELEF pin should be tied to ground through a resistance in the range 13k to 90k. DELEF should not be grounded because it could limit the IC lifetime causing a long term failure. An option is to connect the DCM pin to VREF to suppress the switching signals at OUTE and OUTF pins. This will give a marginal reduction in the system noise.

Q2 – the Excel spreadsheets for the UCC28950, UCC28950-Q1, UCC28951 and UCC28951-Q1 are identical.

Q3 – I’d tend to refer the poster to the datasheet – but that may come across as being a bit harsh. For debug, I would always suggest applying VCC to the controller and then slowly increasing the voltage to the power stage from 0V to about 20V or so, then ‘taking a good look at the waveforms’ before increasing it further in steps – maybe to 50V, then 75V then 100V etc making sure at each stage that key waveforms are ok. The key is to avoid turning the power stage on at 400V and then wonder why it blew up.

Q4 – The controller will run at Dmax when VCC is applied, the CS signal is not necessary.

Q5 – Soft start time – around 50ms or so is reasonable.
Delay times at 6 and 7 – I’d guess that 300ns is a reasonable starting point. This is one of the things to be adjusted as the user SLOWLY increases Vin.


Thanks

REFERENCE:

7.4 Device Functional Modes

• Latch-off mode. Connect a resistor between the SS pin and VREF. The UCC28951-Q1 will then latch off if the controller enters Current Limit mode. (1)

1. Current mode control and voltage mode control are mutually exclusive as are master and slave modes.

Question #1 -- IF A RESISTOR IS CONNECTED BETWEEN Vref AND SS / EN Pin #5 AND THE CS Pin #15 EXCEEDS 2V, THE IC WILL BE SHUT DOWN. THEN WOULD THIS BE A MEANS TO LIMIT THE CURRENT THRU THE QA, QB, QC & QD SWITCHES?

Question #2 -- IS THIS SHUTDOWN SELF RESETING OR WOULD IT REQUIRE A MANUAL RESET?

Question #3 -- WOULD YOU BRIEFLY EXPLAIN THIS FUNCTIONAL MODE IN MORE DETAIL?

Question #4 -- THE UCC28951-Q1 DATASHEET SHOWS NO SCHEMATIC REFERENCE TO THIS RESISTOR NOR DOES THE DATASHEET SUPPLY ANY EQUATION TO SUPPORT THIS MODE. IS THERE AN EQUATION TO SUPPORT THE DETERMINATION OF THE CORRECT VALUE OF THIS RESISTOR VALUE?

Question #5 -- Figure 55. Daughter Board Schematic DOES SHOW A RESISTOR (Rd) THAT IS CONNECTED IN PARALLEL TO THE Css CAPACITOR FROM Pin #5 (SS /EN) TO GROUND. I AM CONFUSED. WOULD YOU PLEASE EXPLAIN THE USE OF THIS RESISTOR WHICH THE DATASHEET HAS NO SUPPORT OR EQUATION TO SUPPORT IT.

ALSO NOTE THE TI UCC28950 EXCEL SPREADSHEET DOES NOT SUPPORT ANY RESISTOR TO Pin #5 WHETHER TIED TO Vref OR GROUND.

Question #6 -- IS THERE AN EQUATION TO SUPPORT THIS FUNCTIONAL MODE.

 

REFERENCE:

UCC28951-Q1 DATASHEET, “UCC28951-Q1 Simplified Application”, Pin #5 SS /EN, (Enable)

THIS FIGURE SHOWS AN “ENABLE” TYING TO Pin #5 BEFORE THE Css WHICH IS TIED TO GROUND. THERE IS NO DOCUMENTATION WHICH DEMONSTRATES WHETHER THIS IS A HIGH SIGNAL OR LOW SIGNAL OR THE CURRENT REQUIREMENTS.

Question #7 -- HOW COULD THIS “ENABLE” BE USED IN CONJUNCTION WITH THE UCC28951-Q1 IC?

Hello Eddie

A1/ When the CS pin reaches 2V the PWM cycle is terminated immediately by the Cycle-by-Cycle comparator on the IC. This happens on each switching cycle and will limit the current through the switches QA, QB, QC and QD. This action does not depend on the value of any resistor from SS/EN to VREF. The C-b-C comparator circuit is active during soft start.  If the over current condition persists then the C-b-C comparator will continue to limit the current in the primary switches and at the same time the SS/EN pin will sink a current, IDS - as shown in Figure 42 of the Data Sheet. This current will discharge the SS capacitor and when the voltage at the SS/EN pin falls to 3.6V all switching will cease. The C-b-C comparator provides cycle by cycle current protection, the 3.6V threshold on the SS/EN pin provides a longer term over current protection. The action of this circuit is explained in section  7.3.14 of the DS.  

A2/A3/A4/  Shutdown can be latching or non-latching. The linked document gives more details on how you can modify the system to give latching or non-latching shutdown or continuous operation at current limit.  /cfs-file/__key/communityserver-discussions-components-files/196/8345.UCC2895x-Hiccup-prevention.docx

A5/ There is a note on P16 of the DS stating that an 825k resistor (5% tol) is needed if the controller is configured in Slave mode. The resistor helps prevent the SS/EN pin rising above 4.65V under certain circumstances - this is not a dangerous condition but it does extent the time the system spends in ILIM before shutting down. It also makes the SS ramp of the slave slower than that of the master.

6/ We have not included the equations needed to support the choice of Hiccup, Latching or non-latching behaviour in the Excel spreadsheet. The document I linked above should give you enough information to design the circuit. If it's not clear then please let me know.

7/ The Enable signal is active Low. The normal way to implement it is to use a small signal MOSFET which is controlled by some digital line from a microcontroller. The circuit is shown in the document linked above. The only important thing is that the EN threshold can be as low as 250mV so a Bi-polar transistor may not have a Vce_sat specification low enough to meet this under all circumstances.

A practical implementation of this EN signal is shown in the PMP8740 reference design - the schematic is at /cfs-file/__key/communityserver-discussions-components-files/196/PMP8740-2KW-Rev_5F00_D-Full-Bridge.pdf

Please let me know if you need any more information.

Regards
Colin

Bliss Zhou

THANK YOU COLIN

I AM IMPLEMENTING CHANGES TO THE DESIGN AS DISCUSSED ABOVE. 

THANK YOU FOR ALL YOUR HELP.

 

ED