Hi,
My customer is using LP8758-E0 to supply PLL in 400Gbps optical module. They need to minimize the switching noise of output voltage to achieve better eye diagram. I've suggested adding a snubber at switching node and optimizing the layout.I would like to confirm two questions,
1. Is there any register that can reduce the slew rate of switching on and off?
2. Does the parasitic capacitance of the inductor couple noise from switching node to output? So should I also choose a low parasitic capacitance inductor?
You could suggest any other measure to reduce the output noise.
Thanks.