Hi,
i have here an open loop board UCD3138OL64EWM-031 Rev.A development board. I've been trying to enable the sync rect fuction with soft on enabled.
here is my code:
void init_front_end0(void)
{
#if 1
/*
* This function will enable the dac ramp mode
*/
FeCtrl0Regs.RAMPCYCLE.bit.SWITCH_CYC_PER_STEP = 0; //sets to 1 switching cycle per step (default)
FeCtrl0Regs.EADCDAC.bit.DAC_DITHER_EN = 1; //enable dither
FeCtrl0Regs.RAMPCTRL.bit.RAMP_EN = 1; //enable ramp mode
//FeCtrl0Regs.RAMPCTRL.bit.SYNC_FET_EN = 1; //enable ramp mode in sync fet
>>> when I tried to enable this command, the output of DPWMAs are always LOW, meaning the dac ramp did not proceed and the DPWMBs are always HIGH
>>> when disabled, however, The DPWMAs normally follow the ramp that I created however, the DPWMBs remains LOW.
FeCtrl0Regs.RAMPCTRL.bit.SYNC_FET_RAMP_START = 0; //default, start sync-FET at zero
FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = 0; //Sets the start of dac_ramp value
FeCtrl0Regs.RAMPCTRL.bit.RAMP_SAT_EN = 0;
FeCtrl0Regs.RAMPCYCLE.bit.DELAY_CYCLES = 0; // Set delay cycles to 0
FeCtrl0Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = (int)(8192); // equivalent to half of EADC_DAC ~0.8V
FeCtrl0Regs.DACSTEP.bit.DAC_STEP = 0x100; // Set Ramp Step to 100
FeCtrl0Regs.RAMPCTRL.bit.FIRMWARE_START = 1; //Ramp Start initiated by firmware
#else
FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = (int)(8192); //Sets the start of dac_ramp value
FeCtrl0Regs.EADCCTRL.bit.AFE_GAIN = 3;
FeCtrl0Regs.EADCCTRL.bit.SAMP_TRIG_SCALE= 0; //Sets eadc firing every 1 sample trigger
#endif
FeCtrl0Regs.EADCCTRL.bit.AFE_GAIN = 3; // Gain X8
FeCtrl0Regs.EADCCTRL.bit.EADC_MODE = 0; //Standard mode, EADC samples based on sample triggers from DPWM module
FeCtrl0Regs.EADCCTRL.bit.SCFE_GAIN_FILTER_SEL = 1; //Enables Switch Cap Noise Filter (Default)
FeCtrl0Regs.EADCCTRL.bit.SCFE_CLK_DIV_2 = 1 ; //Switch Cap Period divide by 2 (Default – 64 ns nominal sample period)
/*
* Enable FrontEnd0
*/
FeCtrl0Regs.EADCCTRL.bit.SCFE_ENA = 1;
FeCtrl0Regs.EADCCTRL.bit.EADC_ENA = 1;
}
void init_loop_mux(void)
{
LoopMuxRegs.DPWMMUX.bit.DPWM0_FILTER_SEL = 0; // use filter 0 for DPWM 0
LoopMuxRegs.DPWMMUX.bit.DPWM1_FILTER_SEL = 0; // use filter 0 for DPWM 1
LoopMuxRegs.DPWMMUX.bit.DPWM2_FILTER_SEL = 0; // use filter 0 for DPWM 2
LoopMuxRegs.DPWMMUX.bit.DPWM3_FILTER_SEL = 0; // use filter 0 for DPWM 3
LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM0_EN = 1; // use DPWM0 for filter0 sample trigger
LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM1_EN = 1; // use DPWM1 for filter0 sample trigger
LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM2_EN = 1; // use DPWM2 for filter0 sample trigger
LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM3_EN = 1; // use DPWM3 for filter0 sample trigger
/*
* Who is slave and who is master?
*/
LoopMuxRegs.DPWMMUX.bit.DPWM0_SYNC_SEL = 0; //DPWM0 is a master
LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0;// sync with DPWM0
LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1; //sync with DPWM1
LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2;// sync with DPWM2
LoopMuxRegs.FECTRL2MUX.bit.DPWM3_B_TRIG_EN = 1; //set DPWM3B up to trigger dither and ramp modules
LoopMuxRegs.FECTRL0MUX.bit.DPWM0_FRAME_SYNC_EN = 1; //Enables DPWM Trigger from DPWM 0 Frame Sync to Front End Control (DAC)
LoopMuxRegs.FECTRL0MUX.bit.DPWM1_FRAME_SYNC_EN = 1; //Enables DPWM Trigger from DPWM 1 Frame Sync to Front End Control (DAC)
LoopMuxRegs.FECTRL0MUX.bit.DPWM2_FRAME_SYNC_EN = 1; //Enables DPWM Trigger from DPWM 2 Frame Sync to Front End Control (DAC)
LoopMuxRegs.FECTRL0MUX.bit.DPWM3_FRAME_SYNC_EN = 1; //Enables DPWM Trigger from DPWM 3 Frame Sync to Front End Control (DAC)
LoopMuxRegs.DPWMMUX.bit.DPWM0_SYNC_FET_SEL = 0; // Front End 0 Ramp output drives DPWM0B SyncFET soft on/off
LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_FET_SEL = 0; // Front End 0 Ramp output drives DPWM1B SyncFET soft on/off
LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_FET_SEL = 0; // Front End 0 Ramp output drives DPWM2B SyncFET soft on/off
LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_FET_SEL = 0; // Front End 0 Ramp output drives DPWM3B SyncFET soft on/off
/*
* This enables sync ramp mode
*/
#if 1
Dpwm0Regs.DPWMCTRL1.bit.SYNC_FET_EN = 1; //enable sync FET mode
Dpwm1Regs.DPWMCTRL1.bit.SYNC_FET_EN = 1; //enable sync FET mode
Dpwm2Regs.DPWMCTRL1.bit.SYNC_FET_EN = 1; //enable sync FET mode
Dpwm3Regs.DPWMCTRL1.bit.SYNC_FET_EN = 1; //enable sync FET mode
#if 0
/*
* This enables sync fet IDE mode
*/
Dpwm0Regs.DPWMCTRL2.bit.IDE_DUTY_B_EN = 1; //enable sync ide mode
Dpwm1Regs.DPWMCTRL2.bit.IDE_DUTY_B_EN = 1; //enable sync ide mode
Dpwm2Regs.DPWMCTRL2.bit.IDE_DUTY_B_EN = 1; //enable sync ide mode
Dpwm3Regs.DPWMCTRL2.bit.IDE_DUTY_B_EN = 1; //enable sync ide mode
#endif
#else
Dpwm0Regs.DPWMCTRL1.bit.SYNC_FET_EN = 0; //enable syncFET mode
Dpwm1Regs.DPWMCTRL1.bit.SYNC_FET_EN = 0; //enable syncFET mode
Dpwm2Regs.DPWMCTRL1.bit.SYNC_FET_EN = 0; //enable syncFET mode
Dpwm3Regs.DPWMCTRL1.bit.SYNC_FET_EN = 0; //enable syncFET mode
#endif
}
Thanks.
