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LP3972: Technical Question about the LP3972

Part Number: LP3972

Hello team,

I have another question about the LP3972: If we are only using Buck 1 and Buck 2, and we do not want to use Buck 3 (and even prefer Buck 3 will not operate its switching at all, if possible)-

how should we connect its inputs? Should we connect GND to its VinBuck3 pin? And what about its FB3 pin? (maybe we should connect +5V there?)

and what about Vin inputs of LDO's in case we do not want to use?

could you please advise, thanks in advance.

Best regards,

Shai

  • Hi Shai,

    Inputs can be connected to GND, outputs can be left floating.

    Best Regards,

    Rick S.

  • Rick,

    Thanks for your inputs, I will detail the questions below a little farther:
    1. What do we do with unused LDO's on the LP3972- note that in the old LP3970 we connected the Vin of such unused regulators to +5V, and added 1uF capacitors on their outputs? Maybe we do not need that?
    2. If we will not use Buck 3 ( VinB3, FB3, and SW3) - we will connect to pins as you mentioned above correct?

    Thanks a lot and regrads.
    Shai
  • Hi Rick,

    Can you please advise back, I not sure about the Buck3 because if the FEEDBACK input detects GND it might try to raise the output voltage?

    Thanks in advance.

    Best regards,

    Shai

  • Hi Shai,

    1. What do we do with unused LDO's on the LP3972- note that in the old LP3970 we connected the Vin of such unused regulators to +5V, and added 1uF capacitors on their outputs? Maybe we do not need that?

    • Using +5V and external capacitors is an ideal configuration, where software can still disable the regulators. Connecting VIN LDOx to GND physically prevents an output voltage on VOUT LDOx, and removes the need for external capacitors, but will indicate power is not OK according to the status registers.


    2. If we will not use Buck 3 ( VinB3, FB3, and SW3) - we will connect to pins as you mentioned above correct?

    • Yes, you can connect VINB3 to GND, and FB3 can be connected to GND or floating, and SW3 can be left floating.
    • VOUT will not rise if VINB3 is not connected.

    Please also disable the regulators with software just to be thorough and potentially reduce quiescent currents.

    Best Regards,

    Rick S.

  • Hi Rick,

    Thank you very much.

    But since I do not want to change software from the original product that used the LP3970- and since in default- (as discussed earlier in this correspondence)- the Enable signals for all the blocks in the LP3972 are the common external signals Sys-Enable and Power-Enable as they were in the LP3970- those unused blocks will be Enabled together with the active blocks even if I do not need them, so it will probably cost me some wasted quiescence current, but I am not worried about that because this instrument is operated from the AC voltage and not from a battery.

    To summarize- I will connect the +5V to inputs of unused LDO's, add 1uF caps on their outputs, and connect GND to input Vinb3 of the third buck, and nothing to its output or FB- and let them all be enabled because they are enabled by the Sys-En or Pwr-En signals.

    Since I am not reading the Low-Volt_PD status by software (the original software also didn't read that)- and since the LP3972 does not have the nVDD_FLT output signal for the MCU that the LP3970 had- I intend to use the rise of VCC_CORE (=1.4v from Buck1  enabled by PWR_EN) to signal the MCU- (via some transistors for level changing, and using the line that was reading the nVDD_FLT from the old LP3970)- that the low voltages were activated, so that the MCU could than de-assert its nRESET_OUT signal and start running the application. I believe that should work fine. What do you think?

    BR

    Shai

  • Hi Rick,
    Could you please advise the below thanks,

    ---
    But since I do not want to change software from the original product that used the LP3970- and since in default- (as discussed earlier in this correspondence)- the Enable signals for all the blocks in the LP3972 are the common external signals Sys-Enable and Power-Enable as they were in the LP3970- those unused blocks will be Enabled together with the active blocks even if I do not need them, so it will probably cost me some wasted quiescence current, but I am not worried about that because this instrument is operated from the AC voltage and not from a battery.

    To summarize- I will connect the +5V to inputs of unused LDO's, add 1uF caps on their outputs, and connect GND to input Vinb3 of the third buck, and nothing to its output or FB- and let them all be enabled because they are enabled by the Sys-En or Pwr-En signals.

    Since I am not reading the Low-Volt_PD status by software (the original software also didn't read that)- and since the LP3972 does not have the nVDD_FLT output signal for the MCU that the LP3970 had- I intend to use the rise of VCC_CORE (=1.4v from Buck1 enabled by PWR_EN) to signal the MCU- (via some transistors for level changing, and using the line that was reading the nVDD_FLT from the old LP3970)- that the low voltages were activated, so that the MCU could than de-assert its nRESET_OUT signal and start running the application. I believe that should work fine. What do you think?

    Thanks in advance with regards,
    Shai
  • Hi Shai,

    This should be OK.

    Best Regards,

    Rick S.

  • Hi Rick,

    Thank you very much for your kind support.

    A new question: in the LP3972 datasheet- in Table 2- for the type LP3972SQ-A514 they specify some of the outputs as "(D)= Regulator DISABLED during start-up", while for other types- for example for LP3972SQ-I514- those outputs are marked with "(E)=ENABLED during startup". I do not understand this status "During Startup"- because those regulators ENABLE input is always the SYS_EN signal- so the operation of those LDO's should only be dependent on the SYS_EN input, isn't that so??? I have chosen the A514 type because I thought that those LDOs should not be enabled from the beginning, and that only after SYS_EN arrives they should start to operate- was I wrong? Should I choose the LP3972SQ-I514 instead? And if indeed the SYS_EN is the LDO's Enable input in all types- what is the difference between (D) and (E)?
    what was the situation in the old LP3970SQ-45 concerning this function of the (D) and (E)? Where the LDO outputs "enabled" or "disabled" during startup there? Because we are replacing the obsoleted LP3970SQ-45 to the LP3972, and would like to keep same functionality without touching the software, since the original software did not communicate with the LP3970 at all (they did not use the SDA/SCL pins there even though they were connected- they only trusted the Default state of the LP3970).

    Thanks and regards,
    Shai
  • Hi Shai,

    The I514 should be used if i2c access is not an option and you require LDO2, LDO3, and LDO4 to enable with SYS_EN.

    The D indicates the regulators are disabled, controlled by register 0x12:

    "Output Voltage Enable Register 2 (OVER2) 8h’12"

    For the A514 version, these registers are factory programmed with a value of 0, but can be enabled using I2C.

    The I514 version has these registers factory programmed with a value of 1, and do not need I2C to be enabled with the SYS_EN pin.

    Best Regards,

    Rick S.

  • Rick, thank you very much for your detailed answer.
    Superb support.

    Regards,
    Shai
  • Hello Rick,

    Thank you for your support on the LP3972 so far.

    I just want to confirm I fully understood Wake-up and Pwr_On and functionality:

    · We intend not to use the I2C control bus and trust the default state of the LP3972SQ-I514.

    · We do not use a Battery connected to Vin_BU_Batt pin- instead we will connect the +5V as an input there as well (as we did with the LP3970 in the original version of this board).

    · Since we do not use a battery we do not need to activate the battery charger using pin nCHG_EN/GPIO1.

    · We want that the PMU to automatically start the Initial Cold Start Power On Sequence when an input voltage is connected to Vin_BU_Batt (5V in our case).

    · We have an external reset circuit that applies an active low pulse when the +5V input first rises. And we connect this reset# signal to nRSTI pin of LP3972 (as we did with the LP3970 in the original version of this board).

    · Pins SYS_EN, PWR_EN, nRSTO, and nBAT_FLT are connected to the Marvel Processor PXA270.



    So here are the connections we intend to apply for the input control pins- please confirm that it will automatically start up as I described above:

    1. We intend to connect PWR_ON to GND.

    2. We intend to connect nTEST_JIG to High (+5V)

    3. We intend to connect SPARE pin to GND.

    4. We intend to connect nCHG_EN/GPIO1 to High (+5V)

    -Please confirm if these four suggested connections to the control pins are correct for our desired mode of operation.

    Thanks in advance
    Best regards,
    Shai
  • Hi Shai,

    That is correct. PWRON, nTEST, and SPARE are only used for the EXT_WAKEUP signal. nCHG_EN can be tied high.

    Best Regards,

    Rick S.

  • Rick. Thank you very much for great support especially for such an old chip.

    Regards,
    Shai