LM5119: 60V DC-DC Buck Controller Problem

Hello,
The current sense lines are sensitive to noise (which increases at higher input voltages).
Try improving the filter circuit by increasing R39, R42, R48, and R52 to 100 Ohms each.

Also, we recommend that the CRamp (C43, C65) be less than 2nF.
Here is a useful tool to help choose components for LM5119 designs:
www.ti.com/.../lm25119-5119quick-calc

We have done some adjustments and testing these days and the result is negative :-(

First, we increased R39, R42, R48, and R52 to 100 Ohms each, and CRamp (C43, C65) be less than 2nF. The problem is the same as before which is shown below.

1. VIN=30VDC, VOUT=12V, Load=2A, board runs 15 hours without problem.

2. VIN>30VDC, VOUT=12V, Load=2A, the output voltage changes from 12V to 8V and then comes back to 12V, and repeats in this way.

Second, we used the calculator to adjust all the components value on the board. The calculated result and the associated schematics are attached. The calculator recommends that the frequency should be 750kHz which is the upper limit of LM5119. We changed the RT to 6K. And the testing result is as follows.

1. VIN=16V-60V, VOUT measured is only 5V.

Third, we reduce down the frequency to 321kHz (RT=15K). The resting result is as follows.

1. VIN=16V-60V, VOUT measured is 12.5V without load. But works abnormally with load 2A.

It seems that we haven't caught the right direction. Help please.

LM(2)5119 QuickStart ICC Modified.xlsx.pdfLM5119-12V.pdf

Hello,

There is E-Cap only for input cap. please add 10uF(or 5pcs 2.2uF) ceramic cap in parallel with E-cap, and try to minimize the switching loop.

Regards,

Stone

Hi,

With the help of local Avnet FAE, we finally make the board work. We have removed 4 MOSFETs and the LM5119 can drive the residual 4 MOSFETs now. The output voltage is right now.

However, the chip LM5119 and inductor and the board are very hot (cannot touch by finger) even with no load. The input voltage is 30~60V and the input current is measured as 0.1A.

We have connected the vout to VCC1 and VCC2 through a diode, and divide the vout using two resistors to VDDIS to disable the inside LDOs.

The final schematic is as follows. Not that for the input capacitors, we have put some 0.1uF capacitors.

Pleas help to solve the hot problem.

8053.LM5119-12V.pdf

Hello,

Can you check below items?
1. Check if Vout is oscillating and if the switching jitter is larger. This is to check if the loop is stable.
2. Use oscilloscope probe to check if there is overlap between high-side Vgs and low-side Vgs. This is to check if there is weak short through between high-side FET and low-side FET.

If possible, can you provide layout design file? Just want to check if the problem is related to layout.

Thanks
Qian