Other Parts Discussed in Thread: LM74610-SQEVM
Hello,
The circuit we are designing is the input to a DCDC module. We have used the LM74610-Q1 in the return path to protect from reverse polarity. As of now the circuit is as it is shown in the schematic picture attached.
When checking the voltage drop across the Vcap capacitor the timing does not match the behavior described in the datasheet. The datasheet says that the fall time should be 5.7 seconds and the rise time should be 0.1175 seconds when using a 4.7uF capacitor. As it can be seen in the picture we get 1.22 seconds fall time and 0.034s rise time. Giving a 97.3% duty cycle instead of the 98% that the datasheet says.
Ambient temperature is 25C and the IC gets around 37C after running 10 minutes with 20A through the transistor (the model is IAUT240N08S5N019ATMA1).
In one of the boards we discovered that the timing was 500ms fall time and 40ms rise time, giving a 92.3% duty cycle. This was solved by changing the LM74610-Q1.
What could be the cause of the wrong timing? What could have caused that the IC broke?
Thanks in advance
Best regards, Inigo