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TPS650864: TPS6508640 Questions for ZU6

Satoshi Yone
Expert 3600 points
Part Number: TPS650864
Other Parts Discussed in Thread: TPS544C25,

Hi, Team,

We have questions for the TPS6508640 + ZU6. Could you please support?

◆ Sequence of VCCINT and VCCBRAM
VCCINT will be generated by "TPS544C25". My customer plans to use "6.3 TPS6508640 Design and Settings". In the sequence diagram, "VCCINT" has risen after "VCCBRAM". The device specification of Zynq ZU6 recommends launching "VCCINT" first. We think it is different from the recommended sequence, is it correct?

◆ About I/O power supply
The following voltages are considered for the I/O power supply of Zynq.
・ PS side I/O power supply "VCCO_PSIO": +3.3 V
・ IO side power supply of PL side “VCCO_HDIO”: + 3.3V “VCCO_HPIO”: + 1.8V
In the data sheet "6.3 TPS6508640 Design and Settings",
"VCCO_HDIO" uses "LDOA2" to generate "0.7 V to 1.5 V".
"VCCO_HPIO" uses "LDOA3" to generate "0.7V to 1.5V".
As this does not meet the specifications if
"VCCO_PSIO" and "VCCO_HDIO" are generated from BUCK1
"VCCO_HPIO" is considered to be generated from BUCK5,
Sequence specification can not be satisfied. Could you tell me the recommended power supply configuration when I/O voltage is the above specification? Should they control by inserting a load switch etc. separately?

◆ About power supply for DDR memory
They plan to adopt DDR3L. Please tell me how to set VDDQ: + 1.35V and VTT: 0.675V.
(Is it the setting of CTL1 and CTL2 pins?)

Best Regards,
Satoshi Yone

  • 0
    TI__Mastermind 20590 points
    Hi Yone-san,

    Today is a public holiday in the US. This thread has been assigned and will be addressed next week after the holiday.
  • 0 in reply to Scott Monroe
    TI__Expert 4155 points
    Yone-san,

    Here are the answers to each of your questions. For both questions 1 and 2 you can follow the power map in the TPS650864 datasheet (figure 6-3).

    1. You are correct that VCCINT is recommended to be powered on before VCCBRAM, however it is not required for one to be turned on before the other. The reason our design does not follow this is because the GPO that is controlling the external VCCINT rail can't be programmed with a shutdown delay. Because there is no shutdown delay we instead turn on BUCK2 first, and have GPO1 programmed to monitor BUCK2_PG. This ensures that the shutdown sequence doesn't violate Xilinx spec by having VCCINT and VCCBRAM shut down after all of the other rails.

    2. I do not believe VCCO_HDIO or VCCO_HPIO need to be sequenced in any way. Both the LDOA2 and LDOA3 rails just need to be enabled through I2C communication by setting the LDOA2_DIS and LDOA3_DIS bits to 1. By default LDOA2 will output 1.5V, which can power VCCO_HDIO and LDOA3 will output 1.2V, which can power VCCO_HPIO.

    3. You are correct about the DDR3L voltages. When CTL1 & CTL2 are high BUCK6 will output 1.35V and VTT_LDO will output 0.675V.