Is there a good reason why HS and HB are on the opposite side of the device to the SW pin?
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We haven't seen any issues with the clamping function. The clamp circuitry limits the bootstrap refresh operation to ensure that the high-side gate driver overdrive does not exceed 5.4 V. On the other hand, the low side FET has no clamping function.
Hope this helps.
Regards,
Serkan