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TPS24751: Clarification of ppad electrical connections

Janet Stillman
Prodigy 80 points
Part Number: TPS24751
Other Parts Discussed in Thread: TPS25982

Can you please clarify the electrical connectivity of the two PPAD thermal pads on the TPS24751? I get from the datasheet instructions that we should connect the larger pad to the fet drain plane, and perhaps ground to the smaller of the two thermal pads. But the eval module shows both pads connected to ground planes. Does this mean you have  a good thermal connection to the die through a thin oxide or other passivation layer, but no electrical connection, so we can use any pcb plane we want for connecting to either pad, as long as we provide a nice thermal path? Is that also the case for the area between the pads, so we can safely have a single plane underneath the entire center of the chip?

Thanks.

  • 0
    TI__Guru** 105611 points
    Hi Janet,

    Welcome to E2E!
    The two thermal pads should NOT connect together. Same has been followed in the EVM. can you please highlight where they are connected together in eval module.
    What is your application use case ? can you look at TPS25982 device ?

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Prodigy 80 points

    Rakesh,

    Ah, yes, on more careful review I see that the two pads are not connected together on the eval design. Can you clarify what they are connected to electrically? Should the smaller pad always be ground, and the larger connect to drain?

    The TPS25982 does look like a nice chip, but I don't see it available from our usual distributors, and generally avoid preliminary parts that we can't easily get reliably. I see samples are available on request, but am concerned about the risk of relying on that.

    Regards,

    Janet

  • 0 in reply to Janet Stillman
    TI__Guru** 105611 points
    Hi Janet,

    yes, smaller pad should be grounded and the larger pad should be connected to the drain (other end of sense resistor)

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    TI__Guru** 105611 points
    Hi Janet,

    If there are no other questions. Please close this thread as resolved.

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    Prodigy 80 points

    Rakesh,

    I do actually have a new question. After working through the timer considerations, I'd like some advice on the safety of having a very long timeout. I'd like to have 3 seconds. It looks like the time at startup while the fet is turning on and the fet gate is charging is a few ms, so the time with a high Vds is in the ms range. From the SOA curve and the datasheet example, it seems the designers would like us to set the timer to assume that the fet might linger in that not-fully-on stage for longer under some conditions, and so they set the timer to have a time that eliminates the possibility of lingering in the high-vds,high-current mode. But the time I'd like to have for system performance reasons -- the actual purpose of including this chip -- is providing 10 A for up to 3 s before starting to fold back and cut off that high current. So a ms to 10s of ms timeout is not useful in this application. So: given that normally the fet gate will charge up within a few ms, is it reasonable to assume that the device will be in the high-vds/high-current regime briefly enough that it is not necessary to use the timer to avoid overheating the fet on startup?

    Best,

    Janet

  • 0 in reply to Janet Stillman
    TI__Guru** 105611 points
    Janet,

    Concern is during startup into fault (for example, waking up into output short ->Figure 39). This situation won't allow you to use higher timeout due to SOA limitation.

    you would need device like TPS2477x having dual timers, where startup and fault timeouts can be set independently.

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    TI__Guru** 105611 points
    Janet,

    Does the above answer your question ?

    Best Regards,
    Rakesh
  • 0 in reply to Rakesh
    TI__Guru** 105611 points
    Hi Janet,

    If there are no other questions. Please close this thread as resolved.

    Best Regards,
    Rakesh