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TINA/Spice/TPS2493: !PG pin and 9mS deglitch

Part Number: TPS2493
Other Parts Discussed in Thread: TINA-TI,

Tool/software: TINA-TI or Spice Models

Hi,

The TPS2493 datasheet describes the function of the PG open drain output pin. It states that the !PG pin will be open drain whenever the external FET Vds is > 2.7V, or UVEN is low or UVLO is active. It also then explains the 9mS deglitch timer. The block diagram of the IC shows that the 9mS deglitch is after the comparator which is monitoring Vds, whereas the UVLO and UVEN are inputs which control the enable of the fault logic circuit. 

My question is this:

When I simulate the action of pulling low UVEN whilst the TPS2943 is active and the !PG pin is low (OUT has reached the VCC voltage), at the point at which UVEN goes low, !PG stays low for a further 9mS. Is this actually correct? The block diagram does not indicate entirely clearly how the !PG NFET is managed by the fault logic. The TINA model seems to indicate that the same 9mS de-glitch delay is also associated with changes detected at the UVEN pin and I assume also UVLO. The wording of the datasheet infers that all events that might cause !PG to go open drain are associated with the de-glitch circuit and regardless of the action which triggers !PG to go open drain there will always be 9mS of delay on the !PG pin. The TINA model reflects this inference.

Can you please clarify that this 9mS timer is seen with all events that cause !PG to go open drain.

Thanks

Aidan