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AM3352: Timing Specifications Recommendation for AM335x - VSYS ON after PMIC and WAKEUPn sent to uP

Chris Yorkey
Genius 15265 points
Part Number: AM3352
Other Parts Discussed in Thread: TPS65217,

Sitara Friends & Family,

Our customer has a question regarding Timing Specifications between our AM335x Sitara and corresponding TI PMIC (TPS65217).  See the below graphic which contains timing info per our specifications for most parameters, EXCEPT for that listed for T2 and T3:

Can we offer a Timing Spec like we do for some of the other parameters (T1 T4 etc) such as 50msec < T < 1 Sec) for instance?

Also, please confirm that the nmi_int register location is indeed :  9C0h as defined in AM335x TRM.

TY,
CY

  • 0
    TI__Guru**** 393215 points
    Hi,

    Yes, the conf_nmi register location OFFSET is 9C0h. The rest of your question are related to the PMIC itself, so I am moving this to the PMIC forum.
  • 0
    TI__Mastermind 30280 points
    From the POWER DOWN or OFF state:
    T2+T3 = 55ms (deglitch time of power-on event)

    From the RESET state:
    T2+T3 = 0 to 1s (PMIC is in a 1s loop, waiting for the nRESET pin to be released)

    PMIC Reset is an internal signal, so T2 and T3 cannot be separated into separate times.

    Please refer to Figure 24. Global State Diagram in the TPS65217 datasheet.
  • 0 in reply to Brian Berner
    TI__Genius 15265 points

    Thanks Brian! Very helpful.  We’re getting closer but their SW resource is still unsure how to define the pins in the device tree.   I realize this probably needs to revert back to the Sitara Processors Forum but perhaps Biser & Co can comment also.

    There was a patch to the device tree to support the TPS65217.  I’m thinking we need guidance on how to read the device tree and look for how it hooks to the kernel.  Thanks again for your help or from others in advance.

    Regards,

    Chris

  • 0 in reply to Chris Yorkey
    TI__Mastermind 30280 points

    Chris,

    It looks like a new thread was created and Resolved already. I will Close this thread. It will re-open automatically if you still have a related follow-up question.

  • 0 in reply to Brian Berner
    TI__Genius 15265 points

    Yes, thanks Brian!

    -Chris

  • 0 in reply to Chris Yorkey
    TI__Genius 15265 points
    Hey Brian,

    One last clarification, in terms of PMIC if I may please:

    In referring to the PMIC reset as the external reset pin being manually held low - the customer intends for T2 & T3 (in pic above) to be initiating from the same point, the release of the external PMIC reset. So they are asking how long for SYS (& VLDO in their case) to come up after the PMIC allowed on and how long for the wakeup signal to be sent to AM3352 after the same starting point?

    I have a hard time extracting the info from the global state diagram they provided. Of all the rails and Pgood type signals, there is no mention of WAKEUPn. Maybe they should abstract a bit to T3 + T4 = (50ms < T <5s)?

    Thanks in advance,
    Chris
  • 0 in reply to Chris Yorkey
    TI__Mastermind 30280 points
    Chris,

    Can you share the document that you originally photographed when you asked this question?

    I cannot clearly see T2, T3, and T4 arrows in the image. If I can see the start/end points of the Tx times, then I can answer more clearly.
  • 0 in reply to Brian Berner
    TI__Genius 15265 points

    Brian,

    See if these work?  Thanks!!

    -Chris

  • 0 in reply to Chris Yorkey
    TI__Mastermind 30280 points

    The time from nRESET released high to SYS turning on can be anywhere from 30ms (tDG,nRESET) to 1s. The reason is because the RESET state in the state machine is a 1s loop. Every time the 1s timer expires, the state of nRESET is checked. If nRESET == Low, the PMIC stays in RESET for 1s more. If nRESET == High, the PMIC begins to transition to the ACTIVE state.

    These pictures show a condensed version of your power-up sequence, showing the PMIC turning on after nRESET is released high at different points in the 1s loop.

    There is no delay from when SYS goes high to when nWAKEUP goes low, as shown in this scope shot.

  • 0 in reply to Brian Berner
    TI__Genius 15265 points
    Brian,

    VERY helpful. We've had a chance to review this with our customer and feel pretty confident they are moving forward now. For now, we can consider this closed and I will provide any additional input as time progresses.

    Thanks again and very much appreciated!

    Regards,
    Chris