TPS544C20: is there any leakage current if VIN and ADD do not apply?

Fujiwara-san,

The PGOOD pin is an open drain FET. The leakage current with 5 V applied to it is about 7.5 uA typical.

Unfortunately, I do not have any data for the CTRL, DATA and CLK pins. I would expect the leakage current for those pins to be in the nA range Typically it will be the gate input to a MOS logic.

John-san,

Thanks for answer. I want to know whether these currents to path to other pins. For example, leakage current will be flow to VDD pin through ESD diode. Would you tell it for each?

Best Regards,
Fujiwara

Fujiwara-san,

As stated, the PGOOD leakage is FET drain to source for the pull down FET. For the CNTL, DATA and CLK it should be minuscule leakage into the logic gate (gate of MOS structure). We don't have data on it as it is not tested, but the assessment came from our DMTS. He also mentioned there may possibly be an additional path if there is an internal pull up, although the pull up should be "off" if there is no power to VDD or VIN. Why do you need to know it? What is your concern?