According to Spec. P.11 & P12, it show the waveform of "GS data write" & "FC/BC/DC write".
When GS data write, the LATCH is default low, and will issue a rising pulse (L->H->L) after 288 bits GS data.
When FC/BC/DC write, the LATCH is default high, and will issue a falling pulse (H->L->H) after 288 bits command & FC/BC/DC data.
If i want to set FC/BC.DC data after GS data update, the LATCH should go High before issue FC/BC/DC data.
But it will lead to a rising edge of LATCH which may cause latch unknown data.
what's the correct waveform of that scenario?
