TPS65218D0: VnPUC at Battery-Backup Supply Power-Path

Ninomiya-san,

PUC is an abbreviation for Power-Up Condition. It is similar to POR (power-on reset). It is an internal definition for the voltage at which the VIN voltage is above the minimum threshold to power the backup domain of the TPS65218D0 PMIC but is still below VUVLO+VHYST.

The images in section 5.3.1.12 Battery-Backup Supply Power-Path (Figures 5-17 through 5-20) show how the device behaves when the main input voltage (VIN) is removed and the FSEAL == 1b such that the Coin Cell remains on to provide power to VSYS_BU, DCDC5, and DCDC6.

VINT_LDO is well defined when VIN>=2.5V, where VINT_LDO is regulated to 2.5V +/- 2%, but as VIN falls to <2.5V, the PUC becomes false.

Therefore, VnPUC is the approximate voltage you would measure at VINT_LDO when FSEAL==1b and the Coin-Cell is the only supply available.

When VINT_LDO transitions from 2.5V to 2.3V (VnPUC), the voltage supply for DCDC5 and DCDC6 also switches over to the Coin Cell supply. As long as VCC>=2.2V, DCDC5 and DCDC6 will stay in regulation but there will be a noticeable change from the main supply to the backup supply and VINT_LDO will no longer be regulated to 2.5V

This is one of the power-saving features of the TPS65218D0, and I am not 100% sure why VnPUC was added to the datasheet without defining the parameter, but I hope my answer has helped you understand the PMIC better.

Ninomiya-san,

I tested on the bench to see which case is true, and I must admit that my test confirms your statement: INT_LDO begins to decline from 2.5V to 2.3V as VIN goes below 2.5V and continues to less than 2.3V and eventually reaches GND (0V) potential.

I captured this on an oscilloscope, along with DCDC6 voltage.

Although INT_LDO does not remain at 2.3V, it is clear that DCDC6 stays on at 1.8V when FSEAL==1b.

Since INT_LDO is an internal power supply for the TPS65218D0, it does not matter what the voltage is on this pin as long as DCDC5/DCDC6 stay on.

It appears, based on your testing and my testing, that these diagrams (Figures 5-17 through 5-20) in the TPS65218D0 datasheet are a little misleading.

For now, please consider nPUC to be an internal voltage. When VINT_LDO < 2.3V, VnPUC is still available but it cannot be measured. It is an internal supply that provides a voltage for biasing DCDC5/6 FETs, but it is not a clean supply. INT_LDO requires an external capacitor because this supply needs to be very clean for DCDC1-4 and LDO1. VnPUC does not need to be a clean supply, does not have an external capacitor, and cannot be measured outside the device.