• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 336 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ24650: BQ24650

Dave Whitaker
Prodigy 190 points
Part Number: BQ24650

Hi There,

Please see my questions below..

1) Page 3 of the Data sheet  says MPPSET pin needs to be set to 1.2 volts through a divide network. How can we guarantee this will be 1.2 volts when the input is a solar panel which will
vary over a voltage range ?

2) Page 3 of the Data sheet says that VREF can be used as a pull up for Pins  STAT1 AND STAT 2. This confuses me because I though the pull up for the 2 STAT pins was VIN as labeled in the schematic on page 22.   Is the VIN labelled as "Solar Cell Half Panel"  the same VIN that's used to pull up stat1 and 2 through R7 and R8 ?

3) Please explain the use of the ground with the down-facing arrow and the chassis ground on page 22.    Which ground does the battery connect to and which ground does the solar panel connect to ? 

4) I see no explanation for C9 in the schematic on page 22 . Can you explain it's purpose ?

5) Please indicate from the schematic on page 22 which Capacitors are the input and output as referenced in the calculations on page 23 steps 9.2.2.2 and 9.2.2.3.

6) I've  noticed that the FETs recommended are of the "PowerPAK" dual package design . Is this imperative for frequency and capacitance specifications ?  I was hopping to use 2 descrete D-PAK versions.  Are they acceptable for this application ?  We will probably not be running at 10 Amps but more likely at 2 amps.  Please comment.

Thank  you

Dave

  

  

  • 0
    TI__Mastermind 24075 points

    Hi Dave,
    1. The charger internally regulates at 1.2V, so for MPPSET you just have to set the resistor divider network pulled up to VIN, such that the voltage corresponds to what your solar panel's MPPT is, according to equation 2 in section 8.3.2 of the datasheet. When the voltage sensed is 1.2V, charger will regulate charge current to maintain voltage on MPPSET pin at 1.2V.
    2. STAT can be pulled up to either VIN or VREF. If you pull up to VREF, it is easier to use an MCU to monitor faults, as well as on our EVM, allows you to put a jumper to disable all pull-ups to VREF, allowing you to more accurately measure quiescent current of the charger.
    3. These refer to separate analog grounds and power grounds. For more information you can refer to section 11 Layout Guidelines of the datasheet which give a more detailed explanation on how to route your ground plane.
    4. C9 is an additional parallel capacitor that adds to the output capacitance of the LC output. You can use the calculator tool to determine values of inductor and capacitors to still maintain the recommended LC resonant frequency.

  • 0 in reply to Kedar Manishankar
    TI__Mastermind 24075 points
    Hi Dave,
    5. C6 is input capacitor as mentioned in the d.s and must be placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. C8+C9 make up the total output capacitance.
    6. Yes you can use other FETs. Please refer to section 9.2.2.4 Power MOSFETs selection when deciding parameters for your switching MOSFETs.
  • 0 in reply to Kedar Manishankar
    Prodigy 190 points

    Thanks kedar,

    For #6 I had read the detailed section about FET selection. My question was of a general nature considering the amount of attention to stray capacitance built into the EVM board.  I understand the trade offs between conduction loss and switching loss.  I'm not an expert on FETs but I guess that the  geometry and  foot print alone does  not necessarily dictate  Rds(on)  or the charge/ discharge characteristics  - would that be a safe assumtion to make ?   The only reason I bring this up is that DPaks are a bit easer to replace then the ones called out in the EVM board  ( SI7288DP-T1) .   Replacing the BQ24650 would be  imposable  by hand but at least we could change a Dpak  when it comes to our own layout and design.  

    Dave

  • 0 in reply to Dave Whitaker
    TI__Mastermind 24075 points
    Hi Dave,
    Yes; as long as you are paying attention to the actual FET specifications from its datasheet, you can also draw reasonable assumptions on what losses you might encounter. I don't see any reason why you couldn't change to DPAK on your board design.