TPS56720: schematic review for noise requirement 15mVpp max

LALIT VERMA

Part Number: TPS56720

Hi TI,

We have designed power supply to be used with Clock Multiplier Unit(CMU) inside the PCIe PHY for a custom SoC.

Our noise requirement is 15mVpp max in the frequency range 100Mhz - 500MHz.

Please review the schematic and give suggestions if any modification is required in schematic like inductor value, input and output capacitor values and quantity etc to achieve the noise requirements.

over 5 years ago

0 Sam(MPAA) Zhang over 5 years ago

TI__Mastermind 19080 points

Hi,

The schematic looks good. It just looks the same like our recommended application circuit. The frequency range you care about is 100-500MHz. In this range, there won't be such a big noise. The ripple of switching power supply is in the switching frequency, i.e., 500kHz in this case.

Regards,
Hao

0 RAHUL SHARMA52 over 5 years ago in reply to Sam(MPAA) Zhang

Intellectual 715 points

Hi,

In terms of Vp-p, what would be the maximum switching noise on the output voltage?

Regards

Rahul Sharma

0 Sam(MPAA) Zhang over 5 years ago in reply to RAHUL SHARMA52

TI__Mastermind 19080 points

Hi Rahul,

Well, it depends on the parameter of your inductor and output capacitor. Generally speaking, ripple as small as ~10mV can be achieved. The frequency of ripple equals to the switching frequency.
Load transient may also bring some high frequency noise on the output. However, in the frequency range beyond 100MHz, it won't be a problem.
Any further question, please let us know. Thanks!

Regards,
Hao

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TPS56720: schematic review for noise requirement 15mVpp max