UCD3138: NO ONE ANSWER ME SINCE 2 DAYS AGO ,Questions of CLA PID output

I'm not sure what you mean by YN being valuable. As far as suggestions, there is a long chain of events, and lots of registers to be configured to set up the whole loop from EADC input to DPWM output. I recommend following the sequence that you'll find in our training labs at training.ti.com/ucd3138-digital-power-training-series. What we do in the training, and often in practice, is to use the DPWMs in open loop mode first, then set up the filter in open loop - controlling the filter output by using CPU SAMPLE to force an error input, and after that works do we enable the filter input. That will also lead you through all the bits that need to be set for a simple buck. All of these steps but the last one can be done on the open loop board, so that your FETs are not endangered if something goes wrong.

In an operating system, it's often an unexpected, and maybe improperly handled fault that turns off the DPWMs.

If you could tell me what topology you are using, I could perhaps help with more specific suggestions. Also, it would be helpful to know if the DPWM output runs under some conditions, and not in others.