UCC28780: AAM mode at low output current?

Hello Gerrit,

The UCC28780 ACF controller was designed primarily with notebook chargers and adapters in the 25-100W power range in mind, operating from the typical “universal” ac Input range of 90-265Vac. It can be used for other applications as well, but the Mathcad programs are geared toward the envisioned major application space. I’m not surprised that the programs can’t accommodate more specialized applications such as yours with higher input voltages and larger GaN Fets than usual. Also the timing parameters of the controller are geared toward the major application space, so more trial and error adjustments are needed to make it work in a different space.

That said, the threshold between AAM and ABM is set by Vbur which indirectly sets a peak primary current level at the mode boundary. Since the ACF is fundamentally a flyback topology with some modification to account for the ZVS energy, the primary Ipk is related to output power. As long as Vout is constant, an Iout level translates to a Pout level, which translates roughly to ½*Lm*Ipk^2*fsw.

Of these terms, Lm is fixed and Ipk and fsw are variable. Unfortunately, even if Ipk was fixed, fsw would vary with input line level because the on-time varies with line. So a fixed Vbur to set a fixed Ipk would still result in a variable Pout and Iout with line (due to fsw variations). If operating at the boundary in AAM, a higher line increases fsw which increases Pout (Iout) and the loop would force operation into ABM to maintain regulation. Therefore, I have to conclude that your goal to have an ABM threshold at fixed Iout independent of line cannot be achieved. At least, not without some amount of external compensating circuitry. On the other hand, the usual input range (Vbulk = 80V-400V) is a 5:1 variation, while your application may have a narrower range, being all high-line, so fsw variation (and related Iout variation) for fixed Ipk may not be as bad.
 
Note: for those cases of full load still in ABM (most likely at highest input line), this means that Ipk is too high for the condition and the loop is forced to cut back on the number of pulse (go into burst mode) to reduce the power delivery. You are right, you want reduced Ipk for each switching cycle. The most likely cause of excess Ipk (maybe not matching what is predicted by the Mathcad) is uncompensated propagation delays to turn-off the low-side FET. Ropp is intended to compensate for these delays, but it relies on those delays to be relatively constant with line. If some of the delays vary, for whatever reason, then the value of Ropp that optimizes one area of operation will not be optimal at another.

Turn-off delays have the worst effect at the highest input line. So choosing Ropp for that case may be the best, since delay effects diminish at lower lines even if Ropp is not optimal there. Another option (using external “work-around” circuit) is to artificially increase the signal to CS at highline. An internal current (based on Ivsl) already does this for Ropp, but if it is not enough (I believe this current is internally clamped to 1.5mA) an external current can be introduced to CS for line voltages exceeding some threshold that you select. That external current can be constant or proportional to Vin above the threshold, depending on your needs. Note: a lower Ipk will translate into higher fsw than what you get now and its consequences. If higher fsw is not acceptable, then only higher Lm can give you lower fsw and many other parameters will have to change with it.

It is possible to overcome many limitations of this controller for special cases, however the cost of overcoming these are the addition of external work-around components. The complexity of the work-around usually increases with the sophistication of the work-around’s function. I hope this helps you decide how to proceed.

Regard,
Ulrich