My design uses a LM5175 switcher, runs from an input supply from 6V to 28V nominally; configured to output 8V.
The device runs normally, and power good asserts as normal.
I want to be able to use the power good signal as an early warning of input power loss. As the input supply falls, at some point the LM5175 won't be able to maintain the output voltage and VOUt will start to fall.
As specified, PGOOD should assert above 7.3V and below 8.6V for this design spec, and indeed, as the supply starts to fall below 7.3V , PGOOD starts to go low.
PGOOD is pulled up with 100K to 3.3V rail ( supply is still energised for some time even after VOUt falls due to downstream switcher/caps).
Unfortunately, the PGOOD signal is pulled low very very slowly. It takes 300us to decay to ~0.95V which trips my downstream enable signal.
I'm trying to understand why the signal is pulling low so slowly, when the output should be a NMOS fet , capable of sinking 4.2ma. The pull up current is 33uA - it should easily be able to pull down the signal.
The are two loads on the PGOOD signal, amounting to about 12pf of pin capacitance, so nothing should be holding up the PGOOD signal.
Any ideas, why PGOOD takes so long to decay?
Only theory I have right now is that the input supply has also fallen too far to power the electronics of the device and it can no longer drive the NMOS to pull down the pgood signal. But the switcher is still running and trying to regulate VOUT, so that doesn't seem to make sense.
Can any one confirm if the device can pull PGOOD low faster? or any thoughts what might be amiss in this situation?
