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ISO5451: Active Miller Clamp, when using the external current Buffer circuit

Part Number: ISO5451

Hello,

We are using the TI ISO5451 in an existing gate Driver circuit.

For driving SiC-semiconductors, we would like to add the recommended external current buffer circuit of the datasheet (pic below) to get more peak output current ability.

Is it still possible to use the active miller clamp function of the TI ISO5451 by connecting Pin7 to the gate of the SiC-semiconductor directly?

The clamping becomes active when the gate voltage is below 2V. Could this result in a problem, if the internal clamping device is active without knowing the actual gate voltage at the SiC-semiconductor?

Thank you for your help.

Tobi

  • Hi Tobias,

    Sorry, I cannot see the image you have attached. Can you try to attach it differently?

    You may still use the internal Miller Clamp with the buffer circuit. However, if you are using a negative bias at VEE2, you may be better off just using the pull down of your external buffer since physically closer to the gate of the SiC MOSFET than the internal Miller Clamp. Thus, it may not be necessary to use the clamp in this application.

    Regards,
    Audrey
  • Hi Audrey,

    Thank you for your reply. You are right, somehow the pic was not included. Now you should see it above.

    Good to know, that the miller clamping can still be used. As you wrote, the intention is either to use the miller clamp with a unipolar gate voltage supply, or the pull down BJT and supplying the gate with a bipolar voltage without connecting Pin 7 to the gate.

    Please let me know if you agree or something is incorrect.

    Thank you and best regards,

    Tobi

  • Hi Tobias,

    Yes, it can be done this way. The miller clamp will be most useful if the driver is located very close to the SiC device. If it is far away, there will be parasitics in the current loop of the clamp pin, and thus not be very useful.

    There is also another possibility of connecting an external pnp BJT as an external clamp so that you can place it close to the SiC device. The gate of the pnp can be connected to CLAMP, which measures the gate voltage. When the threshold is reached, then the pnp will pull down the gate to VEE. This would be more effective than the internal FET of ISO5451 if it is much closer to the gate.

    Regards,
    Audrey
  • Hi Audrey,

    Thank you for your detailed Feedback that helps a lot.

    Best regards,

    Tobias