Hello everyone,
I am working on half bridge circuit with input voltage range from 100-800 v and circuit topology is shown below. When I drive the mosfet using gate driver ucc21520 the higher side and lower side gate pulses are good and clean without any noise when I don't apply any input voltage on drain source of both higher and lower side mosfet of half bridge.
But the moment I apply input voltage (100-300v) on the mosfet at power side ( drain to source) the gate pulse on the higher side is offset is getting added up during gate pulse off period but same nature I am not able to see on lower mosfet. Initally I thought of Miller effect but it is only on higher side in lower side gate pulses are clear.
Below I am attaching photos of gate pulses on higher side and lower side. The gate pulse in which there is offset is higher side mosfet and the gate pulse in which pulses are clear without offset are lower side pulses. These nature I am able to see only when I provide drain to source input voltage.
And these offset is increasing with increasing input voltage. Please can I know what is the reason behind this. Waiting for the reply
