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UCC28951-Q1: A OFF timing of synchronous rectification

Part Number: UCC28951-Q1


Hi Experts,

There is an item to set the OFF delay time of synchronous rectification on page 19 of the data sheet. On page 53, there is a comment that "A good place to set these delays is 50% of tABSET.". While a dead-time between A and B is decreasing when a load is increasing, a OFF delay between E and F is increasing when a load is increasing.

Is there any recommended % of load when we should set them as 50%?

If a delay between E and F is larger than a dead-time between A and B, are there any chance that a surge or anything occurs?

Regards,

Uchikoshi

  •  Hello Uchikoshi-san

    Please have a look at the diagrams in the attached. The AB transition is also known as the PA transition (Passive to Active) and is described in slides 1 to 5 with more detail of the SR transition that happens during the PA transition is shown in slide 9, 10. 

    There isn't a direct relation between the primary side delays and those on the secondary side. The most important thing to make sure of is that the SR is turned OFF before the current through it reverses. Slide 1 shows OUTF going low at about 50% of the DELAB time and the I_QF is still positive at that time, positive current means that the current is flowing in the channel from source to drain of the MOSFET. When QF turns off this current transitions into the body diode of the MOSFET.

    If the SR is turned off after before QB is turned on then that won't be a problem - PROVIDED that the current in the SR is still positive at that time.

    /cfs-file/__key/communityserver-discussions-components-files/196/PSFB-Switch-Transitions.pptx

    The reason we suggest an initial setting of 50% is that it is a good place to start the process of iterating to a final value. I would use the DELAB setting at 100% of load to do this - so if DELAB = 200ns then set DELEF time to 100ns.

    Regards

    Colin