BQ76200: FET orientation...common sources?

Hi Jeffrey,
In general the bq76200 does not work with a common source configuration with the discharge FET closest to the battery. CHG is driven from the BAT pin voltage when off to BAT + VDDCP when on. The DSG pin is driven from the PACK pin level when off to BAT + VDDCP when on. At higher battery voltages the CHG pin would pull the gate of the charge FET above its abs max. For example in your simulation when V(chrg) is the only high signal the FET gate voltage would be 24V while the source could be 0V which will damage a conventional FET.
While you may find situations where this configuration would work we would not typically recommend it.

Hi Jeffrey,
Ciss is the typical simple parameter used for calculating the CVDDCP for the BQ76200, but as you indicate it is Qg which has more effect on switching. Since the AUIRF part has higher Ciss and Qg than the CSD19536 used in the apnote, it certainly may be more difficult to switch many FETs. While you can scale up the CVDDCP, the internal resistances remain fixed and the external resistances will have a practical limit.
The BQ76200 was not designed to be paralleled. Different parts will have independent delays and UVLO thresholds. While the delays are short the parts could end up switching at different times with with essentially 1 part performing the switching or conflicting with the other device and potentially causing UVLO or load shifting between parts. Some FETs can trade load when paralleled and the small individual gate resistors are a common technique to avoid that, but I don't know of a an approach for paralleling BQ76200's.