BQ27426: Design Capacity write not working

No, you just need to be in cfgupdate mode to enter a new design capacity. Please try with bqstudio and see if it works. If it does, then it might be your timing.

hi there,

we are in cfgupdate mode when we update the design capacity.
We also read back the update of the design capacity correctly BUT this is not reflected if we we read the other parameters like the FullAvailableCapacity().

We have tried added delays around those commands but with no luck.

Anymore ideas?

Thank you,
Mickael

Can you please confirm what rev (fw and hw) of the bq27426 you are using? We will try to replicate it here.

Hi there,

here are what we can read from the chip:
device type: 0x426
firmware version: 0x202

Mickael

Hi there, 

do you have any update for me on this point? 

Not being able to set the Design Capacity is really blocking our validation right now... 

Best Regards,

Mickael

Hi,

Here is some extra data nd some of our code so you can help us. 

We’ve been writing drivers for the BQ27426 and so far everything else works correctly, except for one issue. When we try to set the design capacity it does not correctly update the output of the device when reading SoC etc. Surprisingly, this issue occurs despite us confirming that the  BQ27426 acknowledges the new checksum and us being able to read the new design configuration back from register.

Here is our function that configures Design Capacity based on section 4.1 of SLUUBB0, could anyone spot a mistake?

/**

* \brief Sets design capacity

* \param ctx Pointer to system specific functions

* \param cap Desirable design capacity [mAh]

* \return True on success, otherwise false

*/

bool bBQ274SetDesignCapacity(bq27_ctx_t *ctx, uint16_t cap) {



   // Unsealed the device

   if (!_sbUnsealed(ctx)) return false;



   // Enter cfgupdate mode and return true only if cfgUpdateMode is set in Flags

   if (!bBQ274SetCfgUpdate(ctx)) return false;



   uint32_t ret_n = 0;



   // Enable block data memory control by writing 0x00 into 0x61

   ret_n = _suiWriteRegister(ctx, 0x61, 0);



   // Access state subclass 82 that includes Design Capacity parameter

   ret_n |= _suiWriteRegister(ctx, 0x3E, 0x52);



   // Access data located in offset 0 to 31

   ret_n |= _suiWriteRegister(ctx, 0x3F, 0);



   // Read current memory block checksum

   uint8_t crc= _susReadRegister(ctx, 0x60);



   // Read current Design Capacity configuration

   uint8_t old_msb = _susReadRegister(ctx, 0x4A);

   uint8_t old_lsb = _susReadRegister(ctx, 0x4B);



   // Write new Design Capacity configuration

   ret_n |= _suiWriteRegister(ctx, 0x4A, cap >> 8);

   ret_n |= _suiWriteRegister(ctx, 0x4B, cap & 0x0FF);



   // Calculate new checksum

   uint8_t temp = 255 - crc - old_msb - old_lsb;

   uint8_t new_crc = 255 - (uint8_t)(temp + (uint8_t)(cap >> 8) + (uint8_t)(cap & 0x0FF));



   // Write new checksum.

   ret_n |= _suiWriteRegister(ctx, 0x60, new_crc);



// Here, we have confirmed that bq27426 acknowledges the new checksum and

// we can read the new design configuration back from 0x4A & 0x4B



   // SoftReset the device to exit cfgUpdate mode. It returns when cfgUpdateMode is clear.

   ret_n |= uiBQ274SoftReset(ctx);



   // Sealed the device

   if (!bBQ274Sealed(ctx)) return false;



   // Wait for the initialisation bit in control status

   bBQ274WaitInit(ctx);



   // ret_n is zero on SUCCESS

   return !ret_n;

}

And the signature of _suiWriteRegister function is:

/**

* \brief Writes value into given register

* \param ctx Pointer to system specific functions

* \param reg Target register

* \param value Value

* \return Zero on SUCCESS, otherwise I2C bus-specific error code

*/

static uint32_t _suiWriteRegister(bq27_ctx_t *ctx, uint8_t reg, uint8_t value);

Please, let me know if more code is required to troubleshoot our issue.

Also, we noticed that in section 4.1 of SLUUBB0 page 18, when Design Capacity is read the offset is 6 but when Design Capacity is written the offset is 10. At the same time, 0x4A & 0x4B memory locations are read and written in both cases. Is this a typo? Or we are missing something?

Looking forward to hearing back!

Mickael

Hi Mickael,

I looked at the code, the structure and the data locations seem to be right. So this should work.

One question though, have you tried to do this manually using bqstudio? I guess you overlooked the question in the post I asked you before.

Also, what is your value of design capacity? The max value allowed in df is 8000mAh. Either having cfgupdate reset, or sending 0x41 after doing a cfgupdate, or having the design cap be greater than 8000 can cause this problem.

hey guys, 

This solved our issue... probably worth correcting the datasheet because that cost us a lot of debug time!

Mickael