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TPS74801-Q1: Vbias connected to Vin consumes "high power"?

Doug Vetter
Prodigy 200 points
Part Number: TPS74801-Q1

I'm using this part in the configuration:

Vin = 5V

Vout = 3.3V

The datasheet specifies that Vbias be at least 1.6V higher than Vout.  My configuration satisfies that requirement (with 0.1V to spare) and so I plan to connect Vbias to Vin. 

The issue I have is with this incredibly vague and confusing statement:

-----

Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass FET; therefore VBIAS mustbe 1.6 V above VOUT. Because of this usage, IN and BIAS tied together easily consume huge power.  Pay attention not to exceed the power rating of the IC package.

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I assume the warning applies if the differential is not at least 1.6V.  But if I supply it with 4.9-5.0 volts this warning does not apply and the device will function normally, correct?

  • 0
    TI__Intellectual 1146 points

    Hi Doug,

     

    Given your operating conditions the LDO should perform adequately as long as VIN remains steady at 5V.

     This statement on the datasheet is there to properly address the efficiency of the LDO. What this line is referring to is a contrast to circuits where VBIAS and VIN are separate.  Power dissipation with a separate bias would be:

    PD = [VDOIN* IOUT] + [VDOBIAS*IBIAS]

    Because IBIAS is a max of 2mA, maximum power dissipation of the bias rail is a max of 3.2mW. Dropout from VIN to VOUT will then be limited to a max of 165mV and VIN can be reduced accordingly.

    But in a condition where VBIAS and VIN are tied together, the power dissipation will always be high due to a minimum VDOBIAS of 1.6V. in this case power dissipation is:

    PD = [IBIAS + IOUT] + [VDOBIAS]

    In application with higher current demands, this will decrease efficiency greatly in contrast to an application with separate rails.

    Hope this explains this statement.

  • 0 in reply to Jose Gonzalez Torres
    Prodigy 200 points

    Thanks for your response.  It goes without saying, but your description of the issue should be in the datasheet with further examples of anticipated power consumption and efficiency in each mode.

    The 5V input to this part in my design comes from a switchmode controller (also a TI part), and while I expect it to regulate 5V to a reasonable degree (~2%) I can't accept the design risk and inefficiency of this LDO.  It's one thing to be flexible in support of an external bias voltage, but quite another to destroy the efficiency of the design if I choose not to use that feature.  Looks like I'm searching for another part.