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TPS65950

Gandharva Kumar
Intellectual 1750 points
Other Parts Discussed in Thread: OMAP3503, TPS65950

Hello All,

             The datasheet of OMAP3503 processor is not having the clear information on the vdds_sdi, vdds_dsi, vdds_csi2 and vdds_csib power pins and how it should be connected to TPS65950. Can you please provide the following clarifications ASAP.

 

  1. Can we connect the vdds_csi2 (Dedicated power supply for CSI2 Complex I/O) to the VIO_1V8 (VIO DC-DC Regulator of TPS65950) as like in Beagle Board. Our camera subsystem interface requires 1.8V I/O. In SOM module and Mistral board, this is connected to VAUX4.

 

  1.  
    1. What are the voltage and power specifications for the vdds_csi2
    2. What are the GPIO pins powered by vdds_csi2
    3. Is there any sequencing constraints applicable for this power

 

  1. Can we connect the vdds_csib (Dedicated power supply for CSIb Complex I/O) to the VIO_1V8 (VIO DC-DC Regulator of TPS65950). Our camera subsystem interface requires 1.8V I/O. In all the reference boards, vdds_csib is connected to VIO_1V8

 

  1.  
    1. What are the voltage and power specifications for the vdds_csib
    2. What are the GPIO pins powered by vdds_csib
    3. Is there any sequencing constraints applicable for this power

 

  1. Can we connect the vdds_sdi (Dedicated power supply for SDI I/O cell) to the VIO_1V8 (VIO DC-DC Regulator of TPS65950). In all the three boards, vdds_sdi is connected to VPLL2. We are not using the Display Sub system and the pins are configured as GPIO inputs / outputs

 

  1.  
    1. What are the voltage and power specifications for the vdds_sdi
    2. What are the GPIO pins powered by vdds_sdi. The datasheet specifies gpio_66 to gpio_93 vdds and not giving the vdds_sdi or vdds_dsi
    3. Is there any sequencing constraints applicable for this power

 

  1. Can we connect the vdds_dsi (1.8V analog power supply) to the VIO_1V8 (VIO DC-DC Regulator of TPS65950). In all the three boards, vdds_dsi is connected to VPLL2. We are not using the Display Sub system and the pins are configured as GPIO inputs / outputs

 

  1.  
    1. What are the voltage and power specifications for the vdds_dsi
    2. What are the GPIO pins powered by vdds_sdi. The datasheet specifies gpio_66 to gpio_93 vdds and not giving the vdds_sdi or vdds_dsi
    3. Is there any sequencing constraints applicable for this power
  • 0
    TI__Genius 15100 points

    Hi,

    I got the following information from the OMAP support team -

    •  If CSI2 and/or VDAC are not used, then respectively ground VDDS_CSI2 and/or VDDA_DAC with ~5_to_10k resistance.
    •  If MMC1 and SIM are not used, then ground VDDS_MMC1 and VDDS_SIM with ~5_to_10k resistance.
    •  If MMC1 and/or SIM is used, then VDDS_MMC1 must be equal to VDDS_SIM. (even if only one function is used, both should be supplied with the same voltage)
    •  If SDI and/or DSI and/or CSIb are not used, then it is recommended to connect them to 1.8V VDDS.

    Hope this helps.

  • 0 in reply to Gandhar Dighe
    Intellectual 275 points

    Gandhar

    In the newer revision of the OMAP3503 datasheet, SPRS505C, the VDDS_CSI2, VDDS_SDI, VDDS_DSI and VDDS_CSIb power and ground pins are not listed.  These pins are now lumped in with the VDDS pins and VSS and are just labeled as VDDS or VSS.  If you refer to Table 2-28 in section 2.4.8 of the datasheet, SPRS505C, these pins are not listed.  VDDS_CSI2, pin  AG20 - is now VDDS and VDDS_SDI, pin AE27 is now VDDS and VDDS_CSIb, pin H28 is now VDDS and VDDS_DSI, pin AG21 is now VDDS.  The grounds for these pins are lumped in with the VSS pins. 

    Thanks

    Gary