• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 219 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS50601A-SP: PWRGD output low

Ryan.Bishop
Expert 3900 points
Part Number: TPS50601A-SP
Other Parts Discussed in Thread: TPS7A4501-SP,

Hello,

The PWRGD pin is spec to have a minimum output LOW voltage of 0.3V, under the test condition that the pin is sinking 2mA.

We are trying to use the PWRGD pin to drive the /SD pin of the TPS7A4501-SP, which has a threshold voltage as low as 0.15V when transitioning from HIGH-to-LOW.

In our application, we are expecting the PWRGD pin to sink something more like .6mA, but there is no information in the datasheet to determine how low the current needs to go in order to guarantee the PWRGD output is <0.15V to sufficiently drive the other IC's /SD pin low.

  1. Any guidance you can give us on how to proceed?
  2. Also, what voltage is EN internally pulled up to? Since the EN abs max is 5.5V, I assume it isn't pulled up to VIN/PVIN since that might exceed 5.5V.

Thank you!

Regards,
Ryan B.

  • 0
    TI__Expert 4420 points

    Hi Ryan, the intention of the 2mA test condition in the output low specification for PowerGood in the TPS50601A-SP is to provide customers the value of the internal FET resistance (150 ohms). Therefore, you can then adjust the external pull up resistor value to set the voltage needed to drive the shutdown pin of the TPS7A4501-SP accordingly.

    Regarding your second question, the current source in the EN pin is derived from VIN. The reason why the absolute max. of VIN (7.5V) and the absolute max. for EN (5.5V) is different is due to the different ESD cell ratings used for the pins.

    Thanks,

    JV