TPS54560B: Multiple Devices with Synchronization Mode

Hi,

I have not try this type of configuration before. My concern is that the pull down resistor to GND is probably going to be located close to one of the ICs. Therefore when the clock source is at high Z then the other ICs may not have a local pull down resistor to GND

The design might be ok if the pull down resistor is low enough (50ohm) or the impedance of the driving source is low enough to pull the node low. 

Another idea maybe to use 150 ohm pull down on each IC so that the pull down resistor can be close to each IC? 

But again, i would suggest the configuration be tested / prototype first on an EVM before implementing it into production

Thanks

-Arief

Hi Kato,

Yes, that would be good as long as the buffer can drive all the 50 ohm impedance and the clock high and low pulse is based on the datasheet specification

Thanks

-Arief

Hi,

I think in this case you can either size the termination resistor higher than 50 ohm or make sure that when the clock is off, the buffer output is pulled low. 

Thanks

-Arief

In this case i think as long the SYNC signal maximum and minimum is within the datasheet specification, i think that would be fine the way it is.

Thanks

-Arief