LMG1020: Selection of gate resistor for minimization for Vds ringing

Hi Hitesh,

thanks for reaching out about LMG1020. From your description I am assuming during high-side on time the switch node goes high and in the process overshoots to 2X the bus voltage across the low-side FET Vds. Also you are connecting two LMG1020 in a buck half-bridge configuration in which the high-side LMG1020 is powered with a bootstrap configuration

The link below goes into detail on a few different ways to reduce ringing on FETs. The first thing is to make sure you are seeing the correct peak voltage measurement is to use the pig tail measurement technique with the tip directly on the FETs closest drain point of contact and a close source or ground point for the pig tail to ensure the probe loop inductance is minimal and not affecting the peak voltage. You can also consider optimizing the layout to have lower inductance power loop since the di/dt multiplied by the layout loop inductance L equals the voltage drop or rise across the inductance. The inductance can be reduced by minimizing the power loop placement of the bus capacitors and return path using large traces or planes when possible for example. The turn on dv/dt and therefore di/dt can be slowed down by using a 1-10ohm gate resistor on OUTH or boot resistor in the turn on path. A snubber on the switch node can also be an acceptable solution however reduces efficiency. Let me know if you have any questions while implementing any of these solutions.   

 thanks,

hi Hitesh,

thanks for your follow up,

for gate resistor selection check out the app note below, let me know if you have any questions.

www.tij.co.jp/jp/lit/an/slla385/slla385.pdf

thanks,

Hi Hitesh,

thanks for the update,

I have not come across an app note that helps with the tuning of the gate resistor to minimize Vds overshoot, however its possible that this method of selecting a gate resistor is similar to Vds overshoot as well. Anyhow, I will reach out to the proper apps engineers to see if this can be written in the future. The Vds out of max voltage spec depends on if the overshoot is happening during high-side turn-on to the low-side FET or low-side turn-on making negative voltage and increasing the FETs Vds that way. Assuming the overshoot is happening on the low-side FET its either due to dv/dt or current still conducting during turn-off. If dv/dt is the issue then you can slow down the switch-node with a higher gate resistance on the high-side turn on. The process of finding the right gate resistor to limit the dv/dt and consequently the Vds overshoot voltage is empirical and depends on many factors. Start low and increase the resistance to see the effect while making sure you are still getting the required pulse width and efficiency. You can also reduce the layout loop inductance or you can apply a clamping diode (anti-parallel) to help clamp the Vds voltage of the low-side to an acceptable level. Check out the section 2.2.7 in the LMG1020 TIDA (http://www.ti.com/lit/ug/tidue52/tidue52.pdf) on clamping Vds voltage for protecting the FET. It is referencing in a different topology and It's not in a buck configuration however discusses the advantages and disadvantages of using a clamping diode which can be more effective than a gate resistor in some cases. Let me know if this helps answer your question or you have any more follow ups.

Thanks,