TPS51216-EP: OVP, UVP, and regulation issues

Ben,

The engineers that support this device are out of the office this week.

One of them will reply as soon as possible next week.

Regards,

Wade

Hi Wade,

Thank you for the heads up. I'll check back in next week..

Ben

Hey Ben,

Would you be able to send a schematic?

Is this an issue you recently got on new boards from a previously working project? Or is this a new design in which some boards work and some don't.

A quick way to check if its stability would be to take bode plots, but if you can't do that I would suggest adding a bunch of output capacitance. x2 x5 something like that

This usually allows the circuit to be stable, but run slow.

The one test if you can do it that would really help narrow down the issue, it swap the devices on a "bad" board and "good" board.

This will help see if the issue is because of part variance or board variance. 

Thanks,

Daniel

Hi Daniel,

I can send you the circuit but the schematic is ITAR so let's work that offline. I can send you layout too. However, it is identical to Figure 34 (DDR3, 400-kHz Application Circuit, Tracking Discharge) of the TPS51216-EP datasheet with the following differences:

1. VIN is 5V

2. We only have one low-side FET

3. Q1 and Q2 are CSD17313Q2Q1

4. R5 is 30.1k instead of 49k to set VDDQ to 1.35V instead of 1.5V

5. We have an additional 10uF load on VDDQ (so two ceramic 10uF and one polymer 330uF total)

6. There is an additional ferrite with a ceramic capacitor bank behind it that is decoupling for the DDR chips. I have removed the ferrite to isolate the regulator from the load but behavior didn't change.

These are a set of 3 new boards that have just been powered on. 1 is working and 2 are not. However, the design and layout was reproduced from a known, working set of gerbers. One thing I did notice is that their layout ties GND and PGND pins to the thermal pad, which violates this datasheet note:

CAUTION Do not connect PGND pin directly to this thermal land underneath the package.

What is the side-effect of tying PGND to thermal land?

The problem with slowing down the circuit any further is that this chip allows ~2ms from SMPS operation to OVP / UVP detection function enabling. When I reduced the load capacitance by removing the extra 10uF ceramic capacitor at the load, VDDQ ramped faster but then the IC started going into OVP (got up to ~1.5V when design is set for 1.35V). If I add more capacitance I imagine the ramp will be even slower and we'll continue to go into UVP.

Since this is a DCAP design, what is the behavior if there isn't enough ripple? The ripple does not look like figure 35 of the datasheet, it looks more like an oscillator (red trace below is VDDQ as it is ramping up):

I am going to try to replace the parts on the bad boards and see if it helps. I cannot dissemble the 'good' board since it's currently in use.

Hey Ben,

Your explanation of the schematic is likely enough for now. I would prefer not going through he ITAR setup we have if we don't have to.

The side effect that the datasheet note is trying to avoid is adding PGND noise into the thermal pad which is likely connected to AGND and not PGND.

You add quite a bit of noise to the analog circuitry doing that. Its possible that noise being added into the reference is causing these oscillations.

The behavior you are showing is similar to what can happen if DCAP doesn't get enough ripple too. The behavior is generally erratic oscillations because the device doesn't know where to trip the current quite as well.

There are some ways to inject ripple into the feedback that is covered in this app note:

If you can do it, to disconnect thermal pads in the past for debug, I have added thin pieces of thermal tape that would isolate the thermal pad from PGND. This may allow you to see if the disconnect is the issue. Injecting more ripple to check if its that would be the next step, or simply adding more ripple.

Thanks,

Daniel

Hey Ben,

Did this issue resolve itself?

Thanks,

Daniel

Hi Daniel,

Not yet. I should get the boards back today and then I can test the part replacements. Construction review checked out so leaning towards a bad layout. I plan on doing some rework to test that but I need some time. It will be a couple weeks before I can have results. I will check back when I find the issue.

Thanks, Ben

Hi Daniel,

On one failing board, I replaced both external FETs and the IC (TPS51216) itself and the circuit is now working. Could mean a build issue or design margin issue and related to layout.

On a second failing board, I replaced both external FETs and the IC but instead of the TPS51216, I used the TPS51916 (DCAP2 version) but its still set to DCAP mode with 200k mode pin resistor. However, this board is now going into OVL instead of UVL condition at power-up. In fact, the voltage now raises up to ~3.45V before detecting it's over and shuts down. It stabilizes at 3.45V now which is much higher than before.

I'm going to try changing the mode pin resistor to 1k (DCAP2 @ 500kHz, tracking) and see if that does anything for me.

Thank you,

Ben

Hey Ben,

Something does seem up.

Were you ever able to test injecting current ripple from the inductor to increase the ripple seen by the control mode?

Thanks,

Daniel

Hey Ben,

Has this resolved itself?

Thanks,

Daniel