UCD3138: Update DPWM period by firmware and remove hardware

Jack Tan80

Part Number: UCD3138

Hi UCD expert,

Regarding to below diagram of realizing ZVS and valley switch for PFC, the circuit I highlighted is used to generate sync signal to reset DPWM period.

And in application note, it says "All it does is calculated the Ts based on the equation above and generate a PWM pulse equals to Ts. This PWM pulse will turn on Q2 thus no Syn signal is generated during Ts. Once Ts expires, Q2 turns off, a Syn signal is generated to turn the next cycle MOSFET on at exactly the position of tx. "

Since we already know the Ts and resonant time, I'm just wonder if it possible to used the calculated Ts to just update the period of DPWM that controls Q1, and remove the circuit as I highlighted. Is it possible to realize? And any risk about this?

over 6 years ago

0 Amiel Hussain over 6 years ago

TI__Expert 4070 points

Hello Jack Tan!,

An expert is looking into this and will get back to you.

0 Jack Tan80 over 6 years ago in reply to Amiel Hussain

Mastermind 7120 points

Thanks, Amiel.

0 Bosheng Sun over 6 years ago in reply to Jack Tan80

TI__Expert 7260 points

Jack,

The calculation is based ADC measurement, which is noise sensitive, therefore the calculated tx may have some offset. The hardware circuit is used to correct it.

0 Jack Tan80 over 6 years ago in reply to Bosheng Sun

Mastermind 7120 points

Hi Bosheng,

Thanks for your comments. Can you please help me know how does the hardware circuit correct the error?

In my understanding, the high level of sync signal happens when both Q2 and D2 are turned off. Q2 is controlled by DPWM3, and D2 is passive switch, which turned off while no negative current on Q1.

If calculated Ts is not trusted(caused by noise somehow), and suppose calculation larger than the expected value, that will the position of rising edge of sync signal is not the exact position where current return to 0. In this case, the hardware circuit seems won't have much help on correcting it.

0 Bosheng Sun over 6 years ago in reply to Jack Tan80

TI__Expert 7260 points

Jack, If the calculated tx is shorter than it suppose to be, since switch node voltage is still zero, D2 is on, the sync signal is blocked by D2. It does not help if calculated tx is longer than it suppose to be.

0 Jack Tan80 over 6 years ago in reply to Bosheng Sun

Mastermind 7120 points

Bosheng,

Thanks for your comments. It's clear.

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UCD3138: Update DPWM period by firmware and remove hardware