• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 681 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ76920: External Balancing Circuit

Jeffrey Wright
Expert 2875 points
Part Number: BQ76920
Other Parts Discussed in Thread: TIDA-010030,

Hello;

Would you please confirm that the attached schematic is correct for supporting 4 cells. I was uncertain which VC drives which cell.

Thanks in advance!ExternalBal.pdf

  • 0
    Expert 2875 points

    Example of the reason I ask: TIDA-010030 shows a 76940.VC0 driving the discharge fet for cell1. But in SLUA810 Fig 5., it shows a 76920 using VC1 to discharge Cell1??? are both correct?

    THanks

  • 0 in reply to Jeffrey Wright
    TI__Guru 54715 points

    Hi Jeffrey,

    It can be confusing.  For 4 cells the top cell must be used and VC4 connects to VC3, see table 8-1 in the BQ76920 data sheet. Basically shorting C44. This results in 2 transistor gates connected to the VC4-VC3 node, potentially you could use either one, but you still need C50 and R93, so I think it makes most sense to keep the connection of CELL_5 to R131 and use Q17 and related parts.

    Omit Q16, R127-130, R82, R141, R113 and D17.  Short CELL_3 terminal to CELL_4 so that both Q13 and Q17 have current paths back to the top of the 3rd cell.

    I don't think you need the resistors across the zeners, for example the pull down of R96 is provided by R94.

    The 2 schematics (TIDA-010030 and SLUA810 figure5) are drawn slightly differently for the cell1 FET, but both use VC0 for the gate. The TIDA-010030 has the bottom of capacitor C2 connected to GND as recommended in the data sheet.  SLUA810 figure 5 shows the bottom of capacitor C5 connecting to VC0. It is preferred to have that connection to GND so that a step load on the cells does not push VC0 below GND, but it typically works as drawn.

  • 0 in reply to WM5295
    Expert 2875 points

    Thanks WM5295;

    Round 2: I hope this is correct this time. Note I also removed the gs resistors...don't recall why I put them there anyway. I've left the zeners in for now since all your reference designs and appnotes have them, but if they're really NOT necessary, I'd love to remove them and save $.

    Note I also DNP'd R82 and C44 which should be correct (??)

    Let me know if it's OK this time

    Thanks in advance

    0654.ExternalBal.pdf

  • 0 in reply to Jeffrey Wright
    TI__Guru 54715 points

    Hi Jeffrey,

    This looks correct.  The zeners across the gate-source are for transient protection of the external FETs, one example is http://www.ti.com/lit/pdf/slua749 figure 7.  Whether you need them with a 4S or 5S pack will depend on the FET ratings, their durability and the transients in the design.  

    If BAT- connects to CELL0 I don't think you would need D20.

  • 0 in reply to WM5295
    Expert 2875 points

    Thanks WM5295. 

  • 0 in reply to Jeffrey Wright
    Expert 2875 points

    Hello again;

    As a(nother) sanity check, would you please review this modified schematic and suggest any corrections. The application is 4 cells (still ;-D), but my client want's the board to support 5...for some future tbd product. The idea is to have cell4 tied to cell5 in the wiring harness, with the zero ohm jumper across VC4 and VC3. But since R37 and R38 would be present, do I even need the zero ohm??

    Thanks!cell bus.pdf

  • 0 in reply to Jeffrey Wright
    TI__Guru 54715 points

    Hi Jeffrey,

    The recommendation is to short the IC inputs and have 1 input resistor to the shorted pins.  The EVM user guide does indicate shorting the board terminals works for simple evaluation.  With the board input terminals shorted to provide the path for the balancing current, shorting the inputs (R109) and keeping both resistors (R37 and R38) reduces the resistance which is undesired. Keeping both resistors without the short but with the cap C4 may work, but would allow voltage to develop during balancing which should be harmless and settle back to 0 for measurement.  

    The topology looks OK to me.

  • 0 in reply to WM5295
    Expert 2875 points

    Thanks Willy;

     I looked at the EVM guide, but was left a bit (more) confused. If you would, please help replacing my confusion with a bit of knowledge ;-D)

    Fig 6 in slua747a appears to show a current through the two adjacent filter R's, and for N fets, they say that the gate voltage is derived across the lower R

    "Control for the FET comes from the voltage across one of the Rc input resistors. When P-channel balance FETs are used the upper resistor is used, see Figure 5. When Nchannel balance FETs are used, the lower resistor is used, see Figure 6."

    And in SLVU924D, for 4 cells, they say also to remove R5, which would be the Rf for cell4. And since their cell harness shows cell 4 is connected to "cell5". 

    So, I'm "assuming" that when balancing the top cell ("5"), the control would come via R4 and R6, which would be R42 and R38 (?)

    SO, in my scheme, since the discretes for cell 4 will be DNP, wouldn't it be correct/effective  to simply remove R37, and connect cell 4 to J3.6, and leave J3.5 unused? i.e. omit any jumper in the harness?

    Thanks!

  • 0 in reply to Jeffrey Wright
    TI__Guru 54715 points

    Hi Jeffrey,

    There are usually options on which resistor to use.  The 2 inputs at the IC should be connected together.  This gives 2 paths.

    On the EVM there is a resistor simulator, the resistor for the usused cell must be shorted or there is an extra voltage when the simulator is used.  Shorting at both the board connector and the IC places the 2 input resistors in parallel cutting the resistance in half, so one must be removed.

    In your design you don't have a resistor simulator to consider, but have external balance transistors.  These must have a path for the high balance current back to the cell. So you will likely need to short in the harness or the board.  For considerations in maintenance if the same depot handles 4S and 5S systems and the boards share the same connector, having the short in the harness with the cells may be preferred in case boards get swapped.