Customer is having ESD related issue, which is improved with 100pF cap load on IN_nCC line (at the processor input). How much capacitance load can be put on the IN_nCC signal? What are the risks? They plan to test with 100pF, 220pF, 1nF, and 10nF... but looking for some guidance from Design on what kind of cap loading would be okay on this output. Thank you.