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TPS650864: Question for Layout

Satoshi Yone
Expert 3600 points
Part Number: TPS650864

Hello Team

For "TPS650860 Schematic Checklist, Layout Checklist.xlsx", there is the remarks "Be sure that it does not connect to power plane except at the sense point on output capacitor."

Is it recommended that the pattern is drawn from the positive terminal of the capacitor to pin input? Or is it OK to drew the long pattern from the power plane instead of connecting to the power plane?

Best Regards,
Satoshi Yone

  • 0
    TI__Genius 17380 points

    Hi Yone-san,

    For the FB pins, the goal is to measure the voltage at a stable point close to the load. So we recommend connecting to one of the capacitors on the output of the PMIC / input of the load. Depending on the distance between the two they may be the same or different. The focus of this note is that care should be taken in where the FB is measuring from. It should connect to the VOUT at a single point where voltage accuracy is most critical. For certain processors, they have a voltage sense pin that the FB can be connected to for example. 

    The FB pin can handle long routing trace. For FBVOUT2 / FBGND2 in particular, I have seen routing up to 10 cm away and still have good performance when properly shielded.