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TPS65916: reset issue with AM5716

Francesco Residori
Intellectual 460 points
Part Number: TPS65916
Other Parts Discussed in Thread: AM5716,

Hello,

On my board I have a SItara AM5716 and its PMIC TPS659162RGZR.

Below I show the schematics about PMIC

and reset section of Sitara

AM5716_MCLK is a 20MHz clock and SYS_WARMRESETn is high.

For the connections I followed the Figure 2 of "TPS65916 User's Guide to Power AM571x (SLVUA04D)".

The PMIC RESET_OUT (net PMIC_RESET_OUT) and CPU RSTOUTn (net CPU_RSTOUTn) are always low (all the power supply of the PMIC are correct and the PMIC POWERGOOD is high)..

I put a 4.7Kohm to pull-up the PMIC_RESET_OUT and the behaviour of this net and CPU_RSTOUTn are the following:

From the datasheet of the PMIC (SLVSD09B –MARCH 2016–REVISED MARCH 2017) in the paragraph 5.3.4 Device Power Up Timing, I read: "If the time from VCC to VIO is less than 6 ms, the VIO buffers will be supplied while the OTP is still being initialized, which could cause glitches on any VIO output buffer. Supplying VIO at least 6 ms after supplying VCC ensures that the OTP is initialized and output buffers are held low when VIO is
supplied."

So I connected VIO_IN to V3_3D which is up 26ms after 3.3V, but nothing changed.

All the power supply are correct even though VIO_IN is connected to 3.3V which is the VCCA power supply of the PMIC.

Can you help me with this issue?

Thank you

Best regards

Francesco

  • 0
    TI__Mastermind 30310 points

    Francesco,

    I have assigned this question to the expert on the TPS65916 device and your question will be answered as soon as possible.

    Keep in mind that yesterday was a major US holiday and most people are also taking off of work today. I do not expect that you will get an answer before Monday, July 8th.

  • 0
    TI__Genius 10000 points

    Francesco,

    Can you scope VRTC, GPIO0, GPIO5, and RESET_OUT together?

    Also, can you see if the interrupt pin is going high?

    I would also recommend probing all the other GPIOs to understand if they are stable or toggling like RESET_OUT.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Intellectual 460 points

    Hi Nastasha,

    I made some screenshots of the beaviour as in schematics I sent.

    As you can see the PMIC RESET_OUT is stable HIGH.

    INT is HIGH, too

    and powergood is OK:

    At this time I would expect going up the signal coming from SItara (GPIO1_NRESWARM) but is always LOW:

    If I put a 4.7K pull-up on GPIO1_NRESWARM I have the following effect:

    zoomed view:

    GPIO4 and GPIO2 are always stable HIGH, GPIO3 is always LOW.

    Do I make any mistakes?

    VIO_IN must be separated and delayed from VCCA or can be connected together?

    Thanks.

    Best Regards

    Francesco

  • 0 in reply to Francesco Residori
    TI__Genius 10000 points

    Francisco,

    It looks like you are repeatedly toggling the warm reset (GPIO1). this is an active low signal. Every time NRESWARM is set low, the PMIC will perform a warm reset, which returns all the power rails to the default value and toggles RESET_OUT. If you are not intending to initiate a warm reset, keep this pin high.

    Thanks,

    Nastasha

  • 0 in reply to Nastasha
    Intellectual 460 points

    Nastasha,

    thank you for your support, it was very helpful.

    Finally I found that the SYSBOOT configuration of Sitara was not correct. This was the reason why the NRESWARM was always LOW.

    Now it works.

    I have one last question: can I leave VIO_IN connected to VCCA or do I have to power with V3_3D which is turned on by PMIC_REGEN1?

    Best Regards

    Francesco